XC4VFX20-10FFG672C Xilinx Inc, XC4VFX20-10FFG672C Datasheet - Page 65

• Manufacturer Part Number: XC4VFX20-10FFG672C
• Description: IC FPGA VIRTEX-4 FX 20K 672-FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX20-10FFG672C

• Total Ram Bits: 1253376
• Number Of Logic Elements/cells: 19224
• Number Of Labs/clbs: 2136
• Number Of I /o: 320
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-BBGA, FCBGA
• No. Of Logic Blocks: 19224
• No. Of Macrocells: 19224
• No. Of Speed Grades: 10
• No. Of I/o's: 320
• Clock Management: DCM
• I/o Supply Voltage: 3.45V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V4-ML405-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

DCM Attributes
Table 2-6: DCM Attributes
Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
CLK_FEEDBACK
CLKDV_DIVIDE
CLKFX_DIVIDE
CLKFX_MULTIPLY
CLKIN_DIVIDE_BY_2
CLKIN_PERIOD
CLKOUT_PHASE_SHIFT
DCM Attribute Name
R
A handful of DCM attributes govern the DCM functionality.
applicable DCM attributes. This section provides a detailed description of each attribute.
For more information on applying these attributes in UCF, VHDL, or Verilog code, refer to
the Constraints Guide at:
http://www.support.xilinx.com/support/software_manuals.htm
Determines the type of feedback
applied to CLKFB.
Controls CLKDV such that the
source clock is divided by N.
This feature provides automatic
duty cycle correction such that the
CLKDV output pin has a 50/50
duty cycle always in low-frequency
mode, as well as for all integer
values of the division factor N in
high-frequency mode.
Sets the divisor (D) value of CLKFX.
The CLKFX frequency equals the
effective CLKIN frequency
multiplied by M/D.
Sets the multiply (M) of CLKFX.
The CLKFX frequency equals the
effective CLKIN frequency
multiplied by M/D.
Allows for the input clock
frequency to be divided in half
when necessary to meet the DCM
input clock frequency requirements.
Specifies the source clock period to
help the DCM adjust for optimum
CLKFX/CLKFX180 outputs.
Specifies the phase-shift mode.
Description
www.xilinx.com
String: “1X” or “NONE”
Real:
1.5, 2.0, 2.5, 3.0, 3.5, 4.0, 4.5, 5.0,
5.5, 6.0, 6.5, 7.0, 7.5, 8, 9, 10, 11,
12, 13, 14, 15, 16
Integer: 1 to 32
Integer: 2 to 32
Boolean: FALSE or TRUE
Real in ns
String: “NONE”, “FIXED”,
“VARIABLE_POSITIVE”,
“VARIABLE_CENTER”, or
“DIRECT”
Values
Table 2-6
summarizes all the
1X
2.0
1
4
FALSE
0.0
NONE
DCM Attributes
Default Value
65