XC4VFX20-10FFG672C Xilinx Inc, XC4VFX20-10FFG672C Datasheet - Page 391

• Manufacturer Part Number: XC4VFX20-10FFG672C
• Description: IC FPGA VIRTEX-4 FX 20K 672-FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX20-10FFG672C

• Total Ram Bits: 1253376
• Number Of Logic Elements/cells: 19224
• Number Of Labs/clbs: 2136
• Number Of I /o: 320
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-BBGA, FCBGA
• No. Of Logic Blocks: 19224
• No. Of Macrocells: 19224
• No. Of Speed Grades: 10
• No. Of I/o's: 320
• Clock Management: DCM
• I/o Supply Voltage: 3.45V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V4-ML405-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Table 8-8: OSERDES Attribute Summary
Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
OSERDES Attribute
DATA_RATE_OQ
DATA_RATE_TQ
DATA_WIDTH
SERDES_MODE
TRISTATE_WIDTH
OSERDES Attributes
R
DATA_RATE_OQ Attribute
Defines whether data (OQ) changes at every
clock edge or every positive clock edge with
respect to CLK.
Defines whether the 3-state (TQ) changes at
every clock edge, every positive clock edge
with respect to clock, or is set to buffer
configuration.
Defines the parallel-to-serial data converter
width. This value also depends on the
DATA_RATE_OQ value.
Defines whether the OSERDES module is a
master or slave when using width expansion.
Defines the parallel to serial 3-state converter
width.
Clock Event 2
The reset pulse is deasserted on the rising edge of CLKDIV. The difference in propagation
delay between the two OSERDES causes the SR input to come out of reset in two different
CLK cycles. If there were no internal re-timing, OSERDES1 would come out of reset one
CLK cycle before OSERDES0, which would leave both OSERDES out of sync.
Clock Event 3
The release of the reset signal at the SR input is re-timed internally to CLKDIV. This brings
OSERDES0 and OSERDES1 back into sync.
Clock Event 4
The release of the reset signal at the SR input is re-timed internally to CLK.
Table 8-8
primitive. The table includes the default values.
The DATA_RATE_OQ attribute defines whether data is processed as single data rate (SDR)
or double data rate (DDR). The allowed values for this attribute are BUF, SDR, and DDR.
The default value is DDR. When this attribute is set to BUF, the path from the T1 input to
the TQ output of the OSERDES is completely combinatorial.
lists and describes the various attributes that are available for the OSERDES
Description
www.xilinx.com
Output Parallel-to-Serial Logic Resources (OSERDES)
String: “SDR” or “DDR”
String: “BUF”, “SDR”, or
“DDR”
Integer: 2, 3, 4, 5, 6, 7, 8, or 10. If
DATA_RATE_OQ = DDR,
value is limited to 4, 6, 8, or 10.
If DATA_RATE_OQ = SDR,
value is limited to
2, 3, 4, 5, 6, 7, or 8.
String: “MASTER” or “SLAVE”
Integer: 1, 2, or 4
If DATA_RATE_TQ = DDR,
value is limited to 2 and 4. If
DATA_RATE_TQ = SDR or
BUF, value is limited to 1.
Value
Default Value
DDR
DDR
4
4
MASTER
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