XC4VFX20-10FFG672C Xilinx Inc, XC4VFX20-10FFG672C Datasheet - Page 351

• Manufacturer Part Number: XC4VFX20-10FFG672C
• Description: IC FPGA VIRTEX-4 FX 20K 672-FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX20-10FFG672C

• Total Ram Bits: 1253376
• Number Of Logic Elements/cells: 19224
• Number Of Labs/clbs: 2136
• Number Of I /o: 320
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-BBGA, FCBGA
• No. Of Logic Blocks: 19224
• No. Of Macrocells: 19224
• No. Of Speed Grades: 10
• No. Of I/o's: 320
• Clock Management: DCM
• I/o Supply Voltage: 3.45V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V4-ML405-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

OLOGIC Resources
Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
R
The circuitry that results from instantiating the IDELAYCTRL components as shown is
illustrated in
Instantiating Multiple IDELAYCTRLs without LOC Constraints
Instantiating multiple IDELAYCTRL instances without LOC properties is prohibited. If
this occurs, an error is issued by the implementation tools.
OLOGIC blocks include six storage elements (shown in
registers (TFF1, TFF2, and TFF3) are used for 3-state control. The bottom three registers
(OFF1, OFF2, and OFF3) are used for data output. Both sets of registers are functionally the
same.
RST_NOLOC
REFCLK
Figure 7-19: Mixed Instantiation of IDELAYCTRL Elements
Figure
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7-19.
rst_1
rst_2
rst_n
www.xilinx.com
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all IDELAYCTRL
Replicated for
Instantiated without
REFCLK
RST
REFCLK
RST
REFCLK
RST
REFCLK
RST
REFCLK
RST
REFCLK
RST
IDELAYCTRL_noloc
IDELAYCTRL_noloc
IDELAYCTRL_noloc
Instantiated with
LOC Constraint
LOC Constraint
IDELAYCTRL_1
IDELAYCTRL_2
IDELAYCTRL_n
sites
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RDY
RDY
RDY
RDY
RDY
RDY
Auto-generated
by mapper tool
Figure
rdy_1
rdy_2
rdy_n
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7-20.) The top three
OLOGIC Resources
RDY_NOLOC
ug070_7_19_080104
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