XC4VFX20-10FFG672C Xilinx Inc, XC4VFX20-10FFG672C Datasheet - Page 73

• Manufacturer Part Number: XC4VFX20-10FFG672C
• Description: IC FPGA VIRTEX-4 FX 20K 672-FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX20-10FFG672C

• Total Ram Bits: 1253376
• Number Of Logic Elements/cells: 19224
• Number Of Labs/clbs: 2136
• Number Of I /o: 320
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-BBGA, FCBGA
• No. Of Logic Blocks: 19224
• No. Of Macrocells: 19224
• No. Of Speed Grades: 10
• No. Of I/o's: 320
• Clock Management: DCM
• I/o Supply Voltage: 3.45V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V4-ML405-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
R
Deskew Adjust
The DESKEW_ADJUST attribute sets the value for a configurable, variable-tap delay
element to control the amount of delay added to the DCM feedback path (see
This delay element allows adjustment of the effective clock delay between the clock source
and CLK0 to guarantee non-positive hold times of IOB input flip-flop in the device.
Adding more delay to the DCM feedback path decreases the effective delay of the actual
clock path from the FPGA clock input pin to the clock input of any flip-flop. Decreasing the
clock delay increases the setup time represented in the input flip-flop, and reduces any
positive hold times required. The clock path delay includes the delay through the IBUFG,
route, DCM, BUFG, and clock-tree to the destination flip-flop. If the feedback delay equals
the clock-path delay, the effective clock-path delay is zero.
System-Synchronous Setting (Default)
By default, the feedback delay is set to system-synchronous mode. The primary timing
requirements for a system-synchronous system are non-positive hold times (or minimally
positive hold times) and minimal clock-to-out and setup times. Faster clock-to-out and
setup times allow shorter system clock periods. Ideally, the purpose of a DLL is to zero-out
the clock delay to produce faster clock-to-out and non-positive hold times. The system-
synchronous setting (default) for DESKEW_ADJUST configures the feedback delay
element to guarantee non-positive hold times for all input IOB registers. The exact delay
number added to the feedback path is device size dependent. This is determined by
characterization. In the timing report, this is included as timing reduction to input clock
path represented by the T
includes tap delays in the default setting (red line). The pin-to-pin timing parameters (with
DCM) on the
DCM is in system-synchronous mode.
Source
CLK
System-Synchronous
IBUFG
Virtex-4 Data Sheet
Default Setting
Figure 2-4: DCM and Feedback Tap-Delay Elements
DCM
Feedback Tap Delays
DCMINO
www.xilinx.com
…
Setting (Delay set to zero)
CLKIN
CLKFB
Source-Synchronous
reflects the setup/hold and clock-to-out times when the
parameter. As shown in
CLK0
Data Input
Regulator
V
Power
DCM
CCINT
V
CCO
Figure
DCM Design Guidelines
2-4, the feedback path
D
FF
Q
Figure
UG070_2_04_060608
Into the
V
FPGA
CCAUX
2-4).
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