XC4VFX20-10FFG672C Xilinx Inc, XC4VFX20-10FFG672C Datasheet - Page 191

• Manufacturer Part Number: XC4VFX20-10FFG672C
• Description: IC FPGA VIRTEX-4 FX 20K 672-FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX20-10FFG672C

• Total Ram Bits: 1253376
• Number Of Logic Elements/cells: 19224
• Number Of Labs/clbs: 2136
• Number Of I /o: 320
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-BBGA, FCBGA
• No. Of Logic Blocks: 19224
• No. Of Macrocells: 19224
• No. Of Speed Grades: 10
• No. Of I/o's: 320
• Clock Management: DCM
• I/o Supply Voltage: 3.45V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V4-ML405-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
R
Read Only Memory (ROM)
If two dual-port 16 x 1-bit modules are built, the two RAM16X1D primitives can occupy
two slices in a CLB, as long as they share the same clock and write enable, as illustrated in
Figure
The RAM64X1S primitive occupies two slices. The RAM64X1S read path is built on the
MUXF5 and MUXF6 multiplexers.
Each function generator in SLICEM and SLICEL can implement a 16 x 1-bit ROM. Four
configurations are available: ROM16x1, ROM32x1, ROM64x1, and ROM128x1. The ROM
elements are cascadable to implement wider and/or deeper ROM. ROM contents are
loaded at device configuration.
configuration.
Table 5-4: ROM Configuration
5-8.
128 x 1
256 x 1
16 x 1
32 x 1
64 x 1
ROM
Figure 5-8:
D[0]
D[1]
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Table 5-4
Number of LUTs
16 (2 CLBs)
Two RAM16X1D Placement
RAM16X1D Bit 0
RAM16X1D Bit 1
shows the number of LUTs occupied by each
1
2
4
8
Slice M
DPO[1]
Slice M
SPO[1]
SPO[0]
DPO[0]
ug070_5_08_071504
Reg
Reg
Reg
Reg
CLB Overview
191