XC4VFX20-10FFG672C Xilinx Inc, XC4VFX20-10FFG672C Datasheet - Page 297

• Manufacturer Part Number: XC4VFX20-10FFG672C
• Description: IC FPGA VIRTEX-4 FX 20K 672-FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX20-10FFG672C

• Total Ram Bits: 1253376
• Number Of Logic Elements/cells: 19224
• Number Of Labs/clbs: 2136
• Number Of I /o: 320
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-BBGA, FCBGA
• No. Of Logic Blocks: 19224
• No. Of Macrocells: 19224
• No. Of Speed Grades: 10
• No. Of I/o's: 320
• Clock Management: DCM
• I/o Supply Voltage: 3.45V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V4-ML405-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
BLVDS (Bus LVDS)
CSE Differential LVPECL (Low-Voltage Positive Emitter-Coupled Logic)
R
LVPECL Transceiver Termination
Table 6-35: Allowed Attributes of the LDT I/O Standard
Since LVDS is intended for point-to-point applications, BLVDS is not an EIA/TIA standard
implementation and requires careful adaptation of I/O and PCB layout design rules. The
primitive supplied in the software library for bidirectional LVDS does not use the Virtex-4
FPGA LVDS current-mode driver. Therefore, source termination is required.
shows the BLVDS transmitter termination.
Table 6-36
Table 6-36: Available BLVDS Primitives
LVPECL is a very popular and powerful high-speed interface in many system applications.
Virtex-4 FPGA I/Os are designed to comply with the EIA/TIA electrical specifications for
2.5V LVPECL to make system and board design easier.
The Virtex-4 FPGA LVPECL transmitter and receiver requires the termination shown in
Figure
50Ω transmission lines. The LVPECL driver is composed of two LVCMOS drivers that
IOSTANDARD
CAPACITANCE
DIFF_TERM
IOSTANDARD
CAPACITANCE
BLVDS_25
BLVDS_25
Attributes
Attributes
6-77, illustrating a Virtex-4 FPGA LVPECL transmitter and receiver on a board with
summarizes all the possible BLVDS I/O standards and attributes supported.
IOB
Figure 6-76: BLVDS Transmitter Termination
Specific Guidelines for Virtex-4 FPGA I/O Supported Standards
IBUFDS/IBUFGDS
www.xilinx.com
LOW, NORMAL,
DONT_CARE
165Ω
165Ω
R
R
IBUFDS/IBUFGDS
S
S
LOW, NORMAL,
TRUE, FALSE
DONT CARE
R DIV
140Ω
Z 0 = 50Ω
Z 0 = 50Ω
R DIFF = 100Ω
OBUFDS/OBUFTDS
Primitives
Primitives
BLVDS_25
NORMAL
LDT_25
INX
IN
OBUFDS/OBUFTDS
NORMAL
Unused
IOB
LOW, NORMAL,
DONT_CARE
IOBUFDS
BLVDS_25
+
-
Figure 6-76
ug070_6_74_071904
Data in
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