XC4VFX20-10FFG672C Xilinx Inc, XC4VFX20-10FFG672C Datasheet - Page 176

• Manufacturer Part Number: XC4VFX20-10FFG672C
• Description: IC FPGA VIRTEX-4 FX 20K 672-FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX20-10FFG672C

• Total Ram Bits: 1253376
• Number Of Logic Elements/cells: 19224
• Number Of Labs/clbs: 2136
• Number Of I /o: 320
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-BBGA, FCBGA
• No. Of Logic Blocks: 19224
• No. Of Macrocells: 19224
• No. Of Speed Grades: 10
• No. Of I/o's: 320
• Clock Management: DCM
• I/o Supply Voltage: 3.45V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V4-ML405-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Chapter 4: Block RAM
176
[msb:msb-3]
[msb:msb-3]
WRCOUNT
WRCOUNT
Binary → Gray + 2
IN[3:0]
Binary → Gray + 3
IN[3:0]
Notes:
Resource Utilization
Performance
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
IN
IN
•
•
•
•
In this design, the combinatorial logic delay between flip-flops is never comprised of more
than one LUT. A total of 39 LUTs and 41 flip-flops are used.
The performance of this logic matches the performance of the FIFO16 module for each
speed grade as given in the
OUT
OUT
0000
0001
0011
0110
0111
0101
0100
1100
1101
1111
1110
1011
1010
1011
1001
1000
1000
0000
0001
0011
0010
0110
0111
0101
0100
1100
1101
1111
1110
1010
1011
1001
WRCLK
WRCLK
The FULL flag does not mean that the FIFO is full; it means that half of the sector has
been written into after the ALMOSTFULL flag went true.
Setting and clearing of ALMOSTFULL occurs between two and three WRCLK periods
after equality goes true or false, respectively in
Setting and clearing of the FULL flag is delayed as with the ALMOSTFULL flag.
Clearing of the ALMOSTEMPTY flag occurs between 3 and 4 RDCLK periods after an
equality goes false in
OUT[3:0]
OUT[3:0]
4 LUTs
4 LUTs
RST
Figure 4-33: ALMOSTEMPTY Flag Generation
[3:0]
[3:0]
RAgray[3:0]
D[3:0] Q[3:0]
D[3:0] Q[3:0]
RST
RST
Figure
www.xilinx.com
Virtex-4 Data
4 Synchronizers
[3:0]
[3:0]
4-33.
[1:0]
[1:0]
[3:2]
[3:2]
[1:0]
[1:0]
[3:2]
[3:2]
Sheet.
LUT
LUT
LUT
LUT
= =
= =
= =
= =
Figure
D
D
D
D
D
D
PRE
PRE
PRE
PRE
PRE
PRE
Q
Q
Q
Q
Q
Q
4-32.
UG070 (v2.6) December 1, 2008
Virtex-4 FPGA User Guide
LUT
LUT
LUT
D
D
D
PRE
PRE
PRE
UG070_c4_34_020607
Q
Q
Q
ALMOST
EMPTY
R