XC4VFX20-10FFG672C Xilinx Inc, XC4VFX20-10FFG672C Datasheet - Page 343

• Manufacturer Part Number: XC4VFX20-10FFG672C
• Description: IC FPGA VIRTEX-4 FX 20K 672-FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX20-10FFG672C

• Total Ram Bits: 1253376
• Number Of Logic Elements/cells: 19224
• Number Of Labs/clbs: 2136
• Number Of I /o: 320
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-BBGA, FCBGA
• No. Of Logic Blocks: 19224
• No. Of Macrocells: 19224
• No. Of Speed Grades: 10
• No. Of I/o's: 320
• Clock Management: DCM
• I/o Supply Voltage: 3.45V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V4-ML405-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
R
IDELAYCTRL Locations
IDELAYCTRL Usage and Design Guidelines
IDELAYCTRL modules exist in every I/O column in every clock region. An IDELAYCTRL
module calibrates all the IDELAY modules within its clock region. See
Regional Clocks” in Chapter 1
Figure 7-15
XC4VLX15 device.
This section describes using the Virtex-4 FPGA IDELAYCTRL modules, design guidelines,
and recommended usage.
Instantiating IDELAYCTRL without LOC Constraints
When instantiating IDELAYCTRL without LOC constraints, the user must instantiate only
one instance of IDELAYCTRL in the HDL design code. The implementation tools auto-
replicate IDELAYCTRL instances throughout the entire device, even in clock regions not
using the delay element. This results in higher power consumption due to higher resource
utilization, the use of one global clock resource in every clock region, and a greater use of
routing resources. The signals connected to the RST and REFCLK input ports of the
instantiated IDELAYCTRL instance are connected to the corresponding input ports of the
replicated IDELAYCTRL instances.
In ISE® software 9.1 Service Pack 1 and all later versions of the ISE tool, IDELAYCTRL
instances that are replicated to clock regions where they are not needed are trimmed out of
the design automatically by the ISE tool.
Figure 7-15:
1 Clock Region
IDELAYCTRL
(16 I/O tiles)
illustrates the relative locations of the IDELAYCTRL modules for an
Relative Locations of IDELAYCTRL Modules for an XC4VLX15 Device
Column
Left I/O
www.xilinx.com
for the definition of a clock region.
Center I/O
Column
PMCD
DCM
DCM
DCM
8 I/O tiles
Configuration
ILOGIC Resources
“Global and
ug070_7_15_080104
Right I/O
Column
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