XC4VFX20-10FFG672C Xilinx Inc, XC4VFX20-10FFG672C Datasheet - Page 321

• Manufacturer Part Number: XC4VFX20-10FFG672C
• Description: IC FPGA VIRTEX-4 FX 20K 672-FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX20-10FFG672C

• Total Ram Bits: 1253376
• Number Of Logic Elements/cells: 19224
• Number Of Labs/clbs: 2136
• Number Of I /o: 320
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-BBGA, FCBGA
• No. Of Logic Blocks: 19224
• No. Of Macrocells: 19224
• No. Of Speed Grades: 10
• No. Of I/o's: 320
• Clock Management: DCM
• I/o Supply Voltage: 3.45V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V4-ML405-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

SelectIO Logic Resources
Introduction
ILOGIC Resources
Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
R
This chapter describes the logic directly behind the I/O drivers and receivers covered in
Chapter 6, “SelectIO
Virtex-4 FPGAs contain all of the basic I/O logic resources from Virtex®-II/Virtex-II Pro
FPGAs. These resources include the following:
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In addition, the following architectural improvements have been implemented:
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ILOGIC blocks include four storage elements and a programmable absolute delay element,
shown in
To build an edge-triggered D-type flip-flop, the topmost register (IFF1) is used. Only this
register can optionally be configured as a level sensitive latch. The other three registers
(IFF2, IFF3, and IFF4) are used to build various input DDR registers. See
Overview (IDDR),” page 323
All ILOGIC block registers have a common clock enable signal (CE1) that is active High by
default. If left unconnected, the clock enable pin for any storage element defaults to the
active state.
All ILOGIC block registers have a common synchronous or asynchronous set and reset (SR
and REV signals). The set/reset input pin, SR forces the storage element into the state
specified by the SRVAL attributes. When using SR, a second input, REV forces the storage
element into the opposite state. The reset condition predominates over the set condition.
Table 7-1
Combinatorial input/output
3-state output control
Registered input/output
Registered 3-state output control
Double-Data-Rate (DDR) input/output
DDR output 3-state control
IDELAY provides users control of an adjustable, fine-resolution input delay element.
SAME_EDGE output DDR mode
SAME_EDGE and SAME_EDGE_PIPELINED input DDR mode
and
Figure
Table 7-2
7-1.
Resources”.
describe the operation of SR in conjunction with REV.
www.xilinx.com
for further discussion on input DDR.
Chapter 7
“Input DDR
321