XC4VFX20-10FFG672C Xilinx Inc, XC4VFX20-10FFG672C Datasheet - Page 4

• Manufacturer Part Number: XC4VFX20-10FFG672C
• Description: IC FPGA VIRTEX-4 FX 20K 672-FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX20-10FFG672C

• Total Ram Bits: 1253376
• Number Of Logic Elements/cells: 19224
• Number Of Labs/clbs: 2136
• Number Of I /o: 320
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-BBGA, FCBGA
• No. Of Logic Blocks: 19224
• No. Of Macrocells: 19224
• No. Of Speed Grades: 10
• No. Of I/o's: 320
• Clock Management: DCM
• I/o Supply Voltage: 3.45V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V4-ML405-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Virtex-4 FPGA User Guide
01/04/07
Date
Version
2.0
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Chapter 1, “Clock
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Chapter 2, “Digital Clock Managers
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Chapter 4, “Block
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Chapter 6, “SelectIO
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Chapter 7, “SelectIO Logic
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“I/O Clock Buffer -
BUFRs.
“BUFG VHDL and Verilog
“Regional Clocks and I/O
clock regions.
“Status
“Input Clock
“Reset Input —
“Frequency Synthesizer
monitoring LOCKED.
“Data
Table
“RAMB16 Port Mapping Design
ADDR[A|B] pins to High.
“Synchronous
Deleted SIM_COLLISION_CHECK statements from all templates.
Figure
Table
Table 6-31
“Differential Termination
DIFF_TERM attribute.
“Xilinx
Termination).”
Figure
Table
“IDELAYCTRL
regions.
Table
ports.
Table
Added requirement to wait 8 clock cycles after increment or decrement before
sampling IDELAY.
Figure
Modified timing description to match new
“IDELAY VHDL and Verilog Instantiation
INC, and RST from open to zero (both Verilog and VHDL).
Deleted synthesis translate_off/synthesis translate_on statements
from all IDELAY instantiation templates.
4-11: Corrected typo to ALMOST FULL.
6-1: Updated LVTTL DC voltage specifications.
6-38: Corrected I/O standard name to DIFF_HSTL_II_18_DCI.
7-6: Added “when in Variable mode” to function descriptions of C, INC, and CE
7-9: Added Note (1) to T
Flow”: Added paragraph clarifying ADDR setup/hold requirements.
6-53: Corrected internal termination resistor designation.
6-64: Corrected I/O standard name to DIFF_SSTL2_II.
7-12: Modified to show 8 clock cycle wait time.
DCI”: Added reference to section
Flags”: Corrected descriptions for Clock Events 2, 3, and 4.
and following: Globally corrected OBUFGDS to OBUFTDS.
Requirements”: Clarified when DCM output clocks are deskewed.
Clocking”: Clarified synchronous write/read timing.
RAM”:
Resources”:
Locations”: Reworded description of IDELAYCTRL locations in clock
RST”: Updated RST hold time to 200 ms after clock stabilization.
Resources”:
www.xilinx.com
BUFIO”: Added “in the same region” to BUFIO ability to drive
Resources”:
Characteristics”: Added reference and link to a macro for
Attribute”: Corrected paragraph describing use of
Clocks”: Added reference to the PACE tool for identifying
Templates”: Corrected typo in VHDL template.
IDELAYRESOLUTION
Rules”: Corrected logic level tie for unused
(DCMs)”:
Revision
“Driver with Termination to VCCO/2 (Split
Template”: Changed port map for C, CE,
Figure
.
7-12.
UG070 (v2.6) December 1, 2008