XC4VFX20-10FFG672C Xilinx Inc, XC4VFX20-10FFG672C Datasheet - Page 293

• Manufacturer Part Number: XC4VFX20-10FFG672C
• Description: IC FPGA VIRTEX-4 FX 20K 672-FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX20-10FFG672C

• Total Ram Bits: 1253376
• Number Of Logic Elements/cells: 19224
• Number Of Labs/clbs: 2136
• Number Of I /o: 320
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-BBGA, FCBGA
• No. Of Logic Blocks: 19224
• No. Of Macrocells: 19224
• No. Of Speed Grades: 10
• No. Of I/o's: 320
• Clock Management: DCM
• I/o Supply Voltage: 3.45V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V4-ML405-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
DIFF_SSTL18_II_DCI
DIFF_SSTL18_II_DCI
DIFF_SSTL18_II_DCI
DCI
R 0 = 20
R 0 = 20
R
Figure 6-72: Differential SSTL (1.8V) Class II with DCI Bidirectional Termination
Ω
Ω
+
–
2R
2R
2R
2R
Figure 6-72
differential SSTL Class II (1.8V) with bidirectional DCI termination.
Table 6-30
Table 6-30: Differential SSTL (1.8V) Class II DC Voltage Specifications
VRN
VRP
Notes:
1. V
2. Per EIA/JESD8-6, “The value of V
3. V
4. V
5. V
VRN
VRP
V
Input Parameters
V
V
V
V
V
Output Parameters
V
CCO
TT
IN
ID
ID
IX
OX
the use conditions specified by the user.”
= 2Z 0 = 100Ω
= 2Z 0 = 100Ω
= 2Z 0 = 100Ω
= 2Z 0 = 100Ω
IN
ID
IX
OX
(AC)
(DC)
(DC)
(AC)
(AC)
(AC) indicates the voltage where the differential input signals must cross.
(DC) specifies the allowable DC excursion of each differential input.
(DC) specifies the input differential voltage required for switching.
(AC) indicates the voltage where the differential output signals must cross.
(4)
(1)
(3)
(5)
V
lists the differential SSTL (1.8V) Class II DC voltage specifications.
V
shows a sample circuit illustrating a valid termination technique for CSE
CCO
CCO
= 1.8V
= 1.8V
Specific Guidelines for Virtex-4 FPGA I/O Supported Standards
IOB
www.xilinx.com
REF
Z 0
Z 0
is to be selected by the user to provide optimum noise margin in
IOB
V
CCO
V
CCO
= 1.8V
2R
2R
2R
2R
= 1.8V
–0.30
0.675
0.725
Min
0.25
0.50
1.7
VRP
VRN
VRP
VRN
–
= 2Z 0 = 100Ω
= 2Z 0 = 100Ω
= 2Z 0 = 100Ω
= 2Z 0 = 100Ω
V
CCO
Typ
1.8
–
–
–
–
–
× 0.5
DIFF_SSTL18_II_DCI
DIFF_SSTL18_II_DCI
DIFF_SSTL18_II_DCI
R 0 = 20
+
–
R 0 = 20
ug070_6_70_022406
V
V
V
CCO
CCO
CCO
Ω
Ω
1.125
1.075
Max
1.9
–
+ 0.30
+ 0.60
+ 0.60
293