XC4VFX20-10FFG672C Xilinx Inc, XC4VFX20-10FFG672C Datasheet - Page 394

• Manufacturer Part Number: XC4VFX20-10FFG672C
• Description: IC FPGA VIRTEX-4 FX 20K 672-FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX20-10FFG672C

• Total Ram Bits: 1253376
• Number Of Logic Elements/cells: 19224
• Number Of Labs/clbs: 2136
• Number Of I /o: 320
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-BBGA, FCBGA
• No. Of Logic Blocks: 19224
• No. Of Macrocells: 19224
• No. Of Speed Grades: 10
• No. Of I/o's: 320
• Clock Management: DCM
• I/o Supply Voltage: 3.45V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V4-ML405-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Chapter 8: Advanced SelectIO Logic Resources
394
OSERDES Latencies
OSERDES Timing Model and Parameters
The input to output latencies of OSERDES blocks depend on the DATA_RATE and
DATA_WIDTH attributes. Latency is defined as a period of time between the following
two events: (a) when the rising edge of CLKDIV clocks the data at inputs D1–D6 into the
OSERDES, and (b) when the first bit of the serial stream appears at OQ.
summarizes the various OSERDES latency values.
Table 8-11: OSERDES Latencies
This section discusses all timing models associated with the OSERDES primitive.
Table 8-12
characteristics in the
Table 8-12: OSERDES Switching Characteristics
Setup/Hold
Sequential Delays
Combinatorial
T
T
T
T
T
T
T
T
T
DATA_RATE
OSDCK_D
OSDCK_T
OSDCK_T
OSCCK_OCE
OSCCK_TCE
OSCKO_OQ
OSCKO_TQ
OSCO_OQ
OSCO_TQ
DDR
SDR
describes the function and control signals of the OSERDES switching
Symbol
/T
/T
/T
/T
/T
OSCKD_T
OSCKD_T
OSCKD_D
OSCKC_TCE
OSCKC_OCE
Virtex-4 Data
DATA_WIDTH
www.xilinx.com
10:1
2:1
3:1
4:1
5:1
6:1
7:1
8:1
4:1
6:1
8:1
D input setup/hold with respect to CLKDIV
T input setup/hold with respect to CLK
T input setup/hold with respect to CLKDIV
OCE input setup/hold with respect to CLK
TCE input setup/hold with respect to CLK
Clock to Out from CLK to OQ
Clock to Out from CLK to TQ
Asynchronous Reset to OQ
Asynchronous Reset to TQ
Sheet.
1 CLK cycle
3 CLK cycles
4 CLK cycles
4 CLK cycles
5 CLK cycles
5 CLK cycles
6 CLK cycles
1 CLK cycle
3 CLK cycles
4 CLK cycles
4 CLK cycles
Description
UG070 (v2.6) December 1, 2008
Latency
Virtex-4 FPGA User Guide
Table 8-11
R