XC4VFX20-10FFG672C Xilinx Inc, XC4VFX20-10FFG672C Datasheet - Page 377

• Manufacturer Part Number: XC4VFX20-10FFG672C
• Description: IC FPGA VIRTEX-4 FX 20K 672-FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX20-10FFG672C

• Total Ram Bits: 1253376
• Number Of Logic Elements/cells: 19224
• Number Of Labs/clbs: 2136
• Number Of I /o: 320
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-BBGA, FCBGA
• No. Of Logic Blocks: 19224
• No. Of Macrocells: 19224
• No. Of Speed Grades: 10
• No. Of I/o's: 320
• Clock Management: DCM
• I/o Supply Voltage: 3.45V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V4-ML405-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
R
// synthesis BITSLIP_ENABLE of fwd_clk is
// synthesis DATA_RATE of fwd_clk is
// synthesis DATA_WIDTH of fwd_clk is
// synthesis INTERFACE_TYPE of fwd_clk is
// synthesis IOBDELAY of fwd_clk is
// synthesis IOBDELAY_TYPE of fwd_clk is
// synthesis IOBDELAY_VALUE of fwd_clk is 0;
// synthesis NUM_CE of fwd_clk is 1;
// synthesis SERDES_MODE of fwd_clk is
// Instantiate Master ISERDES for data channel
// 1:10 Deserialization Factor
ISERDES data_chan_master (
// synthesis BITSLIP_ENABLE of data_chan_master is
// synthesis DATA_RATE of data_chan_master is
// synthesis DATA_WIDTH of data_chan_master is
// synthesis INTERFACE_TYPE of data_chan_master is
// synthesis IOBDELAY of data_chan_master is
// synthesis IOBDELAY_TYPE of data_chan_master is
.SHIFTOUT2(),
.BITSLIP(1'b0),
.CE1(1'b1),
.CE2(1'b1),
.CLK(iobclk),
.CLKDIV(clkdiv),
.D(clk_in),
.DLYCE(1'b0),
.DLYINC(1'b0),
.DLYRST(1'b0),
.OCLK(1'b0),
.REV(1'b0),
.SHIFTIN1(1'b0),
.SHIFTIN2(1'b0),
.SR(rst),
);
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.O(),
.Q1(data_internal[0]),
.Q2(data_internal[1]),
.Q3(data_internal[2),
.Q4(data_internal[3]),
.Q5(data_internal[4]),
.Q6(data_internal[5]),
.SHIFTOUT1(shiftdata1),
.SHIFTOUT2(shiftdata2),
.BITSLIP(1'b0),
.CE1(1'b1),
.CE2(1'b1),
.CLK(iobclk),
.CLKDIV(clkdiv),
.D(Din),
.DLYCE(1'b0),
.DLYINC(1'b0),
.DLYRST(1'b0),
.OCLK(1'b0),
.REV(1'b0),
.SHIFTIN1(1'b0),
.SHIFTIN2(1'b0),
.SR(rst),
);
Input Serial-to-Parallel Logic Resources (ISERDES)
"NONE";
"DDR";
4;
"MASTER";
"DEFAULT";
"TRUE";
"NETWORKING";
"NONE";
"DDR";
10;
"DEFAULT";
"TRUE";
"NETWORKING";
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