XC4VFX20-10FFG672C Xilinx Inc, XC4VFX20-10FFG672C Datasheet - Page 316

• Manufacturer Part Number: XC4VFX20-10FFG672C
• Description: IC FPGA VIRTEX-4 FX 20K 672-FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX20-10FFG672C

• Total Ram Bits: 1253376
• Number Of Logic Elements/cells: 19224
• Number Of Labs/clbs: 2136
• Number Of I /o: 320
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-BBGA, FCBGA
• No. Of Logic Blocks: 19224
• No. Of Macrocells: 19224
• No. Of Speed Grades: 10
• No. Of I/o's: 320
• Clock Management: DCM
• I/o Supply Voltage: 3.45V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V4-ML405-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Chapter 6: SelectIO Resources
316
Weighted Average Calculation of SSO
First Scaling Factor (SF1)= L
= 1.0 nH/1.1 nH
= 0.909
Second Scaling Factor (SF2)= V
= 550 mV/600 mV
= 0.917
Third Scaling Factor (SF3)
= V
= 600 mV/((22 pF – 15 pF) × 9 mV/pF) + 600 mV
= 600 mV/663 mV
= 0.905
SSO Allowance= SF1 × SF2 × SF3 × 100%
= 0.909 × 0.917 × 0.905 × 100%
= 75.4%
This section describes the SSO calculation where the SSO contributions of all I/O in a bank
are combined into a single figure.
SSO of an individual bank is calculated by summing the SSO contributions of the
individual I/O standards in the bank. The SSO contribution is the percentage of full
utilization of any one I/O standard in any one bank. For drivers of each I/O standard, the
calculation follows:
For a bank with drivers of multiple I/O standards, the SSO calculation is:
A sample SSO calculation follows. The system parameters used are:
DISTURBANCE_NOM
Bank SSO limit (I/O group n)
= (I/O Standard SSO limit × Equivalent V
SSO Contribution (I/ O group n) = (quantity of drivers)/(Bank SSO limit)
Bank SSO
L
V
C
Device:XC4VLX60 FF1148
Bank:1
I/O Standards, Quantities:
PDS_USER
DISTURBANCE_USER
LOAD_USER
SSTL2_II, 22
LVCMOS25_16 Fast, 6
LVCMOS25_6 Fast, 19
=
(
= 1.1 nH
1 to n
∑
= 22 pF
/((C
)
SSO Contribution n ( )
www.xilinx.com
LOAD_USER
PDS_NOM
= 550 mV
DISTURBANCE_USER
/L
– C
PDS_USER
LOAD_NOM
CCO
/V
/GND pairs in bank)
) × 9 mV/pF) + V
DISTURBANCE_NOM
UG070 (v2.6) December 1, 2008
Virtex-4 FPGA User Guide
DISTURBANCE_NOM
R