XC4VFX20-10FFG672C Xilinx Inc, XC4VFX20-10FFG672C Datasheet - Page 304

• Manufacturer Part Number: XC4VFX20-10FFG672C
• Description: IC FPGA VIRTEX-4 FX 20K 672-FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX20-10FFG672C

• Total Ram Bits: 1253376
• Number Of Logic Elements/cells: 19224
• Number Of Labs/clbs: 2136
• Number Of I /o: 320
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-BBGA, FCBGA
• No. Of Logic Blocks: 19224
• No. Of Macrocells: 19224
• No. Of Speed Grades: 10
• No. Of I/o's: 320
• Clock Management: DCM
• I/o Supply Voltage: 3.45V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V4-ML405-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Chapter 6: SelectIO Resources
304
Table 6-39: Absolute Maximum Undershoot and Overshoot
The clamp diodes offer protection against transient voltage beyond approximately
V
the current going through it. Therefore the clamped level is not fixed and can vary
depending on the board design. The absolute maximum I/O limits might be exceeded
even if the clamp diode is active.
The IBIS models contain the voltage-current characteristics of the I/O drivers and clamp
diodes.
To verify overshoot and undershoot are within the I/O absolute maximum specifications,
Xilinx recommends proper I/O termination and performing IBIS simulation.
Source Termination and LVDCI_33
In general, the I/O drivers should match the board trace impedance to within ±10% to
minimize overshoot and undershoot. Source termination is often used for unidirectional
interfaces. The DCI feature has built-in source termination on all user output pins. It
compensates for impedance changes due to voltage and/or temperature fluctuations, and
can match the reference resistor values. Assuming the reference resistor values are the
same as the board trace impedance, the output impedance of the driver will closely match
with the board trace.
The LVDCI_33 standard is used to enable the DCI features for 3.3V I/O operations. As
shown in
termination function in Virtex-4 FPGA output drivers. The pull-up resistor connected to
VRN and the pull-down resistor connected to VRP determine the output impedance of all
the output drivers in the same bank. The
(DCI)”
Since the LVDCI_33 standard does not offer input termination, source termination must be
implemented on the driver side.
termination resistors to be incorporated on the external device side.
CCO
+ 0.5V and Ground – 0.5V. The voltage across the diode increases proportionally to
section has more details on using DCI.
Figure
V
CCO
3.75
3.45
3.6
3.3
3.0
(V)
6-79, the OBUF_LVDCI_33 primitive is used to implement the source
www.xilinx.com
Maximum Undershoot (V)
Figure 6-79
“Virtex-4 FPGA Digitally Controlled Impedance
–0.30
–0.45
–0.60
–0.75
–1.05
shows the recommended external source
UG070 (v2.6) December 1, 2008
Maximum Overshoot (V)
Virtex-4 FPGA User Guide
4.05
4.05
4.05
4.05
4.05
R