XC4VFX20-10FFG672C Xilinx Inc, XC4VFX20-10FFG672C Datasheet - Page 317

• Manufacturer Part Number: XC4VFX20-10FFG672C
• Description: IC FPGA VIRTEX-4 FX 20K 672-FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX20-10FFG672C

• Total Ram Bits: 1253376
• Number Of Logic Elements/cells: 19224
• Number Of Labs/clbs: 2136
• Number Of I /o: 320
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-BBGA, FCBGA
• No. Of Logic Blocks: 19224
• No. Of Macrocells: 19224
• No. Of Speed Grades: 10
• No. Of I/o's: 320
• Clock Management: DCM
• I/o Supply Voltage: 3.45V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V4-ML405-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
Calculation of Full Device SSO
R
Full Device SSO Example
First, SSO limits for each I/O standard are obtained from
From
package is eight.
The Bank SSO limit is calculated for each I/O standard:
Bank SSO Limit =( # drivers per V
Bank SSO Limit (1)=10 drivers per V
Bank SSO Limit (2)= 8 drivers per V
Bank SSO Limit (3)=18 drivers per V
The SSO contribution of each I/O standard is calculated as:
SSO Contribution = (quantity of drivers)/(Bank SSO limit)
SSO Contribution (1)=22/80= 27.5%
SSO Contribution (2)=6/64= 9.3%
SSO Contribution (3)=19/136= 14.0%
Finally, the bank SSO is calculated:
Bank 1 SSO = SSO contribution (1) + SSO contribution (2) + SSO Contribution (3)
= 27.5% + 9.3% + 14.0% = 50.9%
Three separate criteria must be satisfied for a full device design to be within the SSO limit.
The first criterion ensures the number of simultaneously switching outputs does not
exceed the per-bank limit. The second criterion ensures even distribution of output drivers
across the package. A final criterion ensures overall power system disturbance in the chip
is not excessive. The SSO allowance is used in both of the latter two constraints, taking into
account design-specific parameters. The criteria are as follows:
•
•
•
SSO is computed first on a per I/O bank basis. Next, the average SSO of each adjacent bank
pair is computed. Finally the average SSO is computed for all banks to determine the
effective utilization for the entire package.
A sample calculation of full-device SSO is shown for a Virtex-4 FPGA XC4VLX60 FF1148
package. The subscript NOM denotes a nominal value while the subscript DES denotes a
value for the design under analysis.
I/O Group
SSO for any single bank cannot exceed 100%.
Average SSO of two adjacent banks cannot exceed 105% of SSO allowance.
Package SSO cannot exceed SSO allowance.
Table
1
2
3
6-41, the number of equivalent V
SSTL2_II
LVCMOS25_16 Fast
LVCMOS25_6 Fast
I/O Standard
www.xilinx.com
CCO
CCO
CCO
CCO
/GND pair × 8 V
/GND pair × 8 V
/GND pair × 8 V
/GND pair × 8 V
SSO Limit (Drivers per V
CCO
Simultaneous Switching Output Limits
/GND pairs in Bank 1 for the FF1148
CCO
Table
CCO
CCO
CCO
/GND pairs
/GND pairs= 80 drivers
/GND pairs= 64 drivers
/GND pairs= 136 drivers
10
17
8
6-42:
CCO
/GND Pair)
317