XC4VFX20-10FFG672C Xilinx Inc, XC4VFX20-10FFG672C Datasheet - Page 48

IC FPGA VIRTEX-4 FX 20K 672-FBGA

XC4VFX20-10FFG672C

Manufacturer Part Number
XC4VFX20-10FFG672C
Description
IC FPGA VIRTEX-4 FX 20K 672-FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-4r

Specifications of XC4VFX20-10FFG672C

Total Ram Bits
1253376
Number Of Logic Elements/cells
19224
Number Of Labs/clbs
2136
Number Of I /o
320
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-BBGA, FCBGA
No. Of Logic Blocks
19224
No. Of Macrocells
19224
No. Of Speed Grades
10
No. Of I/o's
320
Clock Management
DCM
I/o Supply Voltage
3.45V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
HW-V4-ML405-UNI-G - EVALUATION PLATFORM VIRTEX-4
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
XC4VFX20-10FFG672C
Manufacturer:
ADVANTEK
Quantity:
314
Part Number:
XC4VFX20-10FFG672C
Manufacturer:
XilinxInc
Quantity:
3 000
Part Number:
XC4VFX20-10FFG672C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC4VFX20-10FFG672C
Manufacturer:
XILINX
Quantity:
1 000
Part Number:
XC4VFX20-10FFG672C
Manufacturer:
XILINX
0
Part Number:
XC4VFX20-10FFG672C
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
Part Number:
XC4VFX20-10FFG672C
0
Chapter 1: Clock Resources
48
BUFGCE and BUFGCE_1 VHDL and Verilog Templates
Verilog Template
Declaring Constraints in UCF File
VHDL Template
The following examples illustrate the instantiation of the BUFGCE module in VHDL and
Verilog. The instantiation of BUFGCE_1 is exactly the same as BUFGCE with exception of
the primitive name.
//Example BUFG module declaration
module BUFG (O, I);
endmodule;
//Example BUFG instantiation
BUFG U_BUFG (
.O(user_o),
.I0(user_i)
);
// Declaring constraints in Verilog
// synthesis attribute LOC of U_BUFG is "BUFGCTRL_X#Y#";
// where # is valid integer locations of BUFGCTRL
INST "U_BUFG" LOC = BUFGCTRL_X#Y#;
where # is valid integer locations of BUFGCTRL
--Example BUFGCE declaration
component BUFGCE
port(
end component;
--Example BUFGCE instantiation
U_BUFGCE : BUFGCE
Port map (
--Declaring constraints in VHDL file
attribute LOC : string;
attribute LOC of U_BUFGCE: label is "BUFGCTRL_X#Y#";
--where # is valid integer locations of BUFGCTRL
output O;
input I;
O: out std_ulogic;
CE: in
I: in
);
O => user_o,
CE => user_ce,
I => user_i
);
std_ulogic
std_ulogic;
www.xilinx.com
UG070 (v2.6) December 1, 2008
Virtex-4 FPGA User Guide
R

Related parts for XC4VFX20-10FFG672C