XC4VFX20-10FFG672C Xilinx Inc, XC4VFX20-10FFG672C Datasheet - Page 46
XC4VFX20-10FFG672C
Manufacturer Part Number
XC4VFX20-10FFG672C
Description
IC FPGA VIRTEX-4 FX 20K 672-FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-4r
Datasheets
1.XC4VFX12-10FFG668C.pdf
(58 pages)
2.XC4VFX12-10FFG668C.pdf
(9 pages)
3.XC4VFX12-10FFG668C.pdf
(406 pages)
Specifications of XC4VFX20-10FFG672C
Total Ram Bits
1253376
Number Of Logic Elements/cells
19224
Number Of Labs/clbs
2136
Number Of I /o
320
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-BBGA, FCBGA
No. Of Logic Blocks
19224
No. Of Macrocells
19224
No. Of Speed Grades
10
No. Of I/o's
320
Clock Management
DCM
I/o Supply Voltage
3.45V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
HW-V4-ML405-UNI-G - EVALUATION PLATFORM VIRTEX-4
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
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Part Number:
XC4VFX20-10FFG672C
Manufacturer:
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Quantity:
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Part Number:
XC4VFX20-10FFG672C
Manufacturer:
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Quantity:
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Part Number:
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Manufacturer:
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Quantity:
20 000
- XC4VFX12-10FFG668C PDF datasheet
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- Download datasheet (6Mb)
Chapter 1: Clock Resources
46
Verilog Template
port(
end component;
--Example BUFGCTRL instantiation
U_BUFGCTRL : BUFGCTRL
Port map (
--Declaring constraints in VHDL file
attribute INIT_OUT
attribute PRESELECT_I0 : boolean;
attribute PRESELECT_I1 : boolean;
attribute LOC : string;
attribute INIT_OUT of U_BUFGCTRL: label is 0;
attribute PRESELECT_I0 of U_BUFGCTRL: label is FALSE;
attribute PRESELECT_I1 of U_BUFGCTRL: label is FALSE;
attribute LOC of U_BUFGCTRL: label is "BUFGCTRL_X#Y#";
--where # is valid integer locations of BUFGCTRL
//Example BUFGCTRL module declaration
module BUFGCTRL (O, CE0, CE1, I0, I1, IGNORE0, IGNORE1, S0, S1);
);
O: out std_ulogic;
CE0: in
CE1: in
I0: in
I1
IGNORE0: in
IGNORE1: in
S0: in
S1: in
);
O => user_o,
CE0 => user_ce0,
CE1 => user_ce1,
I0 => user_i0,
I1 => user_i1,
IGNORE0 => user_ignore0,
IGNORE1 => user_ignore1,
S0 => user_s0,
S1 => user_s1
);
output O;
input CE0;
input CE1;
input I0;
input I1;
input IGNORE0;
input IGNORE1;
input S0;
input S1;
parameter INIT_OUT = 0;
parameter PRESELECT_I0 = "FALSE";
parameter PRESELECT_I1 = "FALSE";
PRESELECT_I0 : boolean := false;
PRESELECT_I1 : boolean := false;
std_ulogic;
std_ulogic;
std_ulogic
std_ulogic;
std_ulogic;
: in
std_ulogic;
std_ulogic;
www.xilinx.com
std_ulogic;
: integer;
UG070 (v2.6) December 1, 2008
Virtex-4 FPGA User Guide
R
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