XC4VFX20-10FFG672C Xilinx Inc, XC4VFX20-10FFG672C Datasheet - Page 161

• Manufacturer Part Number: XC4VFX20-10FFG672C
• Description: IC FPGA VIRTEX-4 FX 20K 672-FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX20-10FFG672C

• Total Ram Bits: 1253376
• Number Of Logic Elements/cells: 19224
• Number Of Labs/clbs: 2136
• Number Of I /o: 320
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-BBGA, FCBGA
• No. Of Logic Blocks: 19224
• No. Of Macrocells: 19224
• No. Of Speed Grades: 10
• No. Of I/o's: 320
• Clock Management: DCM
• I/o Supply Voltage: 3.45V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V4-ML405-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
R
Clock Event 1 and Clock Event 2: Read Operation and Deassertion of Full Signal
During a read operation on a full FIFO, the content of the FIFO at the first address is
asserted at the DO output pins of the FIFO. Three write-clock cycles later, the FULL pin is
deasserted when the FIFO is no longer full.
The example in
respect to read-clock, while clock event 2 is with respect to write-clock. Clock event 2
appears three write-clock cycles after clock event 1.
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•
•
If the rising RDCLK edge is close to the rising WRCLK edge, AFULL could be deasserted
one WRCLK period later.
Clock Event 3 and Clock Event 4: Read Operation and Deassertion of
ALMOSTFULL Signal
Three write-clock cycles after the fourth data is read from the FIFO, the ALMOSTFULL pin
is deasserted to signify that the FIFO is not in the ALMOSTFULL state.
The example in
respect to read-clock, while clock event 4 is with respect to write-clock. Clock event 4
appears three write-clock cycles after clock event 3.
•
•
•
There is minimum time between a rising read-clock and write-clock edge to guarantee that
AFULL will be deasserted. If this minimum is not met, the deassertion of AFULL can take
an additional write clock cycle.
At time T
RDEN input of the FIFO.
At time T
inputs of the FIFO.
At time T
Read enable remains asserted at the RDEN input of the FIFO.
At time T
outputs of the FIFO.
At time T
the AFULL pin.
FCCK_RDEN
FCKO_DO
FCKO_FULL
FCKO_DO
FCKO_AFULL
Figure 4-19
Figure 4-19
, after clock event 1 (RDCLK), data 00 becomes valid at the DO
, after clock event 3 (RDCLK), data 03 becomes valid at the DO
, after clock event 2 (WRCLK), FULL is deasserted.
, before clock event 1 (RDCLK), read enable becomes valid at the
, after clock event 4 (RDCLK), ALMOSTFULL is deasserted at
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reflects both standard and FWFT modes. Clock event 1 is with
reflects both standard and FWFT modes. Clock event 3 is with
FIFO Timing Models and Parameters
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