XC4VFX20-10FFG672C Xilinx Inc, XC4VFX20-10FFG672C Datasheet - Page 35

• Manufacturer Part Number: XC4VFX20-10FFG672C
• Description: IC FPGA VIRTEX-4 FX 20K 672-FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX20-10FFG672C

• Total Ram Bits: 1253376
• Number Of Logic Elements/cells: 19224
• Number Of Labs/clbs: 2136
• Number Of I /o: 320
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-BBGA, FCBGA
• No. Of Logic Blocks: 19224
• No. Of Macrocells: 19224
• No. Of Speed Grades: 10
• No. Of I/o's: 320
• Clock Management: DCM
• I/o Supply Voltage: 3.45V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V4-ML405-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
R
BUFGMUX_VIRTEX4
BUFGMUX_VIRTEX4 is a clock buffer with two clock inputs, one clock output, and a select
line. This primitive is based on BUFGCTRL with some pins connected to logic High or
Low.
BUFGMUX_VIRTEX4 uses the S pins as select pins. S can switch anytime without causing
a glitch. The setup/hold times on S determine whether the output will pass an extra pulse
of the previously selected clock before switching to the new clock. If S changes as shown in
Figure
then the output will not pass an extra pulse of I0. If S changes following the hold time for
S, then the output will pass an extra pulse. If S violates the setup/hold requirements, the
output might pass the extra pulse, but it will not glitch. In any case, the output changes to
the new clock within three clock cycles of the slower clock.
The setup/hold requirements for S0 and S1 are with respect to the falling clock edge
(assuming INIT_OUT = 0), not the rising edge as for CE0 and CE1.
Switching conditions for BUFGMUX_VIRTEX4 are the same as the S pin of BUFGCTRL.
Figure 1-12
Other capabilities of the BUFGMUX_VIRTEX4 primitive are:
•
•
Pre-selection of I0 and I1 input after configuration.
Initial output can be selected as High or Low after configuration.
Figure 1-11
1-12, prior to the setup time T
I1
I0
S
illustrates the timing diagram for BUFGMUX_VIRTEX4.
BUFGMUX_VIRTEX4
I 0
I1
O
S
illustrates the relationship of BUFGMUX_VIRTEX4 and BUFGCTRL.
Figure 1-12: BUFGMUX_VIRTEX4 Timing Diagram
Figure 1-11: BUFGMUX_VIRTEX4 as BUFGCTRL
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T
BCCKO_O
O
BCCCK_S
S
and before I0 transitions from High to Low,
GND
GND
V
V
DD
DD
IGNORE1
CE1
S1
I1
I0
S0
CE0
IGNORE0
T
Global Clocking Resources
BCCKO_O
ug070_1_11_071304
ug070_1_12_080204
O
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