XC4VFX20-10FFG672C Xilinx Inc, XC4VFX20-10FFG672C Datasheet - Page 358

• Manufacturer Part Number: XC4VFX20-10FFG672C
• Description: IC FPGA VIRTEX-4 FX 20K 672-FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX20-10FFG672C

• Total Ram Bits: 1253376
• Number Of Logic Elements/cells: 19224
• Number Of Labs/clbs: 2136
• Number Of I /o: 320
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-BBGA, FCBGA
• No. Of Logic Blocks: 19224
• No. Of Macrocells: 19224
• No. Of Speed Grades: 10
• No. Of I/o's: 320
• Clock Management: DCM
• I/o Supply Voltage: 3.45V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V4-ML405-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Chapter 7: SelectIO Logic Resources
358
ODDR VHDL and Verilog Templates
ODDR VHDL Template
ODDR Verilog Template
The following examples illustrate the instantiation of the OSERDES module in VHDL and
Verilog.
--Example ODDR component declaration
component ODDR
--Example ODDR instantiation
U_ODDR : ODDR
Port map(
//Example ODDR module declaration
module ODDR (Q, C, CE, D1, D2, R, S);
generic(
port(
end component;
);
);
);
output Q;
input C;
input CE;
input D1;
input D2;
tri0 GSR = glbl.GSR;
input R;
input S;
parameter DDR_CLK_EDGE = "OPPOSITE_EDGE";
DDR_CLK_EDGE : string := "OPPOSITE_EDGE";
INIT
SRTYPE
Q
C
CE
D1
D2
R
S
Q => user_q,
C => user_c,
CE => user_ce,
D1 => user_d1,
D2 => user_d2,
R => user_r,
S => user_s
www.xilinx.com
: out std_ulogic;
: in
: in
: in
: in
: in
: in
: bit
: string := "SYNC";
std_ulogic;
std_ulogic;
std_ulogic;
std_ulogic;
std_ulogic;
std_ulogic
:= '0';
UG070 (v2.6) December 1, 2008
Virtex-4 FPGA User Guide
R