XC4VFX20-10FFG672C Xilinx Inc, XC4VFX20-10FFG672C Datasheet - Page 129

• Manufacturer Part Number: XC4VFX20-10FFG672C
• Description: IC FPGA VIRTEX-4 FX 20K 672-FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX20-10FFG672C

• Total Ram Bits: 1253376
• Number Of Logic Elements/cells: 19224
• Number Of Labs/clbs: 2136
• Number Of I /o: 320
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-BBGA, FCBGA
• No. Of Logic Blocks: 19224
• No. Of Macrocells: 19224
• No. Of Speed Grades: 10
• No. Of I/o's: 320
• Clock Management: DCM
• I/o Supply Voltage: 3.45V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V4-ML405-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
Optional Output Register On/Off Switch - DO[A|B]_REG
Clock Inversion at Output Register Switch - INVERT_CLK_DO[A|B]_REG
Extended Mode Address Determinant - RAM_EXTENSION_[A|B]
Read Width - READ_WIDTH_[A|B]
Write Width - WRITE_WIDTH_[A|B]
Write Mode - WRITE_MODE_[A|B]
Block RAM Location Constraints
R
Table 4-5: Port Width Values
This attribute sets the number of pipeline register at A/B output of RAMB16. The valid
values are 0 (default) or 1.
When set to TRUE, the clock input to the pipeline register at A/B output of RAMB16 is
inverted. The default value is FALSE.
This attribute determines whether the block RAM of interest has its A/B port as
UPPER/LOWER address when using the cascade mode. Refer to the
RAM”
NONE.
This attribute determines the A/B read port width of the block RAM. The valid values are:
0 (default), 1, 2, 4, 9, 18, and 36.
This attribute determines the A/B write port width of the block RAM. The valid values are:
0 (default), 1, 2, 4, 9, 18, and 36.
This attribute determines the write mode of the A/B input ports. The possible values are
WRITE_FIRST (default), READ_FIRST, and NO_CHANGE. Additional information on the
write modes is in the
Block RAM instances can have LOC properties attached to them to constrain placement.
Block RAM placement locations differ from the convention used for naming CLB locations,
allowing LOC properties to transfer easily from array to array.
Port Data Width
section. When the block RAM is not used in cascade mode, the default value is
18
36
1
2
4
9
“Operating Modes”
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DOP Bus
<1:0>
<3:0>
NA
NA
NA
<0>
section.
DO Bus
<15:0>
<31:0>
<1:0>
<3:0>
<7:0>
<0>
Block RAM Attributes
“Cascadable Block
INIT / SRVAL
(4 + 32) = 36
(2 + 16) = 18
(1 + 8) = 9
1
2
4
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