XC4VFX20-10FFG672C Xilinx Inc, XC4VFX20-10FFG672C Datasheet - Page 334

• Manufacturer Part Number: XC4VFX20-10FFG672C
• Description: IC FPGA VIRTEX-4 FX 20K 672-FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX20-10FFG672C

• Total Ram Bits: 1253376
• Number Of Logic Elements/cells: 19224
• Number Of Labs/clbs: 2136
• Number Of I /o: 320
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-BBGA, FCBGA
• No. Of Logic Blocks: 19224
• No. Of Macrocells: 19224
• No. Of Speed Grades: 10
• No. Of I/o's: 320
• Clock Management: DCM
• I/o Supply Voltage: 3.45V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V4-ML405-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Chapter 7: SelectIO Logic Resources
334
IDELAY Attributes
IDELAY Timing
Table 7-8
Table 7-8: IDELAY Attribute Summary
IOBDELAY_TYPE Attribute
The IOBDELAY_TYPE attribute sets the type of delay used. The attribute values are
DEFAULT, FIXED, and VARIABLE. When set to DEFAULT, the zero-hold time delay
element is selected. This delay element is used to guarantee non-positive hold times when
global clocks are used without DCMs to capture data (pin-to-pin parameters).
When set to FIXED, the tap-delay value is fixed at the number of taps determined by the
IOBDELAY_VALUE attribute setting. This value is preset and cannot be changed after
configuration.
When set to VARIABLE, the variable tap delay element is selected. The tap delay can be
incremented by setting CE = 1 and INC = 1, or decremented by CE = 1 and INC = 0. The
increment/decrement operation is synchronous to C, the input clock signal.
IOBDELAY_VALUE Attribute
The IOBDELAY_VALUE attribute specifies the initial number of tap delays. The possible
values are any integer from 0 to 63. The default value is zero. The value of the tap delay
reverts to IOBDELAY_VALUE when the tap delay is reset.
Table 7-9
Table 7-9: Input Delay Switching Characteristics
IOBDELAY_TYPE
IOBDELAY_VALUE
T
T
T
T
IDELAYRESOLUTION
ICECK
IINCCK
IRSTCK
IDELAY Attribute
/T
/T
/T
summarizes the IDELAY attributes.
shows the IDELAY switching characteristics.
ICKCE
ICKINC
ICKRST
Symbol
Sets the type of tap
delay.
Specifies the initial tap
setting.
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Description
IDELAY tap resolution
CE pin setup/hold with respect to C
INC pin setup/hold with respect to C
RST pin setup/hold with respect to C
String: DEFAULT, FIXED,
or VARIABLE
Integer: 0 to 63
Description
Value
UG070 (v2.6) December 1, 2008
Virtex-4 FPGA User Guide
Default Value
DEFAULT
0
R