XC4VFX20-10FFG672C Xilinx Inc, XC4VFX20-10FFG672C Datasheet - Page 171

• Manufacturer Part Number: XC4VFX20-10FFG672C
• Description: IC FPGA VIRTEX-4 FX 20K 672-FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX20-10FFG672C

• Total Ram Bits: 1253376
• Number Of Logic Elements/cells: 19224
• Number Of Labs/clbs: 2136
• Number Of I /o: 320
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-BBGA, FCBGA
• No. Of Logic Blocks: 19224
• No. Of Macrocells: 19224
• No. Of Speed Grades: 10
• No. Of I/o's: 320
• Clock Management: DCM
• I/o Supply Voltage: 3.45V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V4-ML405-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
Depth is 3 less than
depth of the FIFO16;
e.g., 509 rather than
512.
R
WIF [9:0]
Depth - ALMOST_FULL_OFFSET
(Design Constant)
WRCLK
RST
ALMOST_EMPTY_OFFSET
(Design Constant)
FASTCLK
RDCLK
Figure 4-28: ALMOSTFULL and ALMOSTEMPTY Signal Generation
For this design to work, the ALMOST_FULL_OFFSET and ALMOST_EMPTY_OFFSET for
the FIFO16 instantiations must be fixed values as shown below:
The FIFO16 configurations supported are 4K x 4, 2K x 9, 1K x 18, and 512 x 36.
Two DCMs can be used to generate the FASTCLK as shown in
In some cases, only one DCM is needed to generate FASTCLK. The FASTCLK signal
should be connected to all instances of module fifo_third_clk_flags in the design.
The output RST signal is connected to all FIFOs and all instances of module
fifo_third_clk_flags. Clock feedback must be specified as NONE on both DCMs
(defparam dcm.CLK_FEEDBACK = “NONE”).
System Reset
defparam fifo16.ALMOST_FULL_OFFSET = 12'h001; // do not change this line
defparam fifo16.ALMOST_EMPTY_OFFSET = 12'h1FE; // set this to FIFO16 depth - 2
(no connect)
Slow Clock
DCM_BASE
CLKIN
CLKFB
RST
LOCKED
www.xilinx.com
A
B
A
B
Figure 4-29: FASTCLK Generator
CLKDV
CLKFX
CLK2X
CLK0
A > B
A < B
(no connect)
Medium Clock
D
D
RST
SET
FIFO16 Error Condition and Work-Arounds
Q
Q
DCM_BASE
CLKIN
CLKFB
RST
D
D
RST
SET
Q
Q
LOCKED
CLKDV
CLKFX
CLK2X
CLK0
Figure
D
D
RST
SET
4-29.
BUFG
Q
Q
ALMOSTEMPTY
ALMOSTFULL
UG070_c4_29_020307
UG070_c4_30_020307
FASTCLK
RST
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