XC4VFX20-10FFG672C Xilinx Inc, XC4VFX20-10FFG672C Datasheet - Page 188

• Manufacturer Part Number: XC4VFX20-10FFG672C
• Description: IC FPGA VIRTEX-4 FX 20K 672-FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX20-10FFG672C

• Total Ram Bits: 1253376
• Number Of Logic Elements/cells: 19224
• Number Of Labs/clbs: 2136
• Number Of I /o: 320
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-BBGA, FCBGA
• No. Of Logic Blocks: 19224
• No. Of Macrocells: 19224
• No. Of Speed Grades: 10
• No. Of I/o's: 320
• Clock Management: DCM
• I/o Supply Voltage: 3.45V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V4-ML405-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Chapter 5: Configurable Logic Blocks (CLBs)
188
Distributed RAM and Memory (Available in SLICEM only)
The configuration options for the set and reset functionality of a register or a latch are as
follows:
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•
•
•
•
•
•
Multiple left-hand LUTs in SLICEMs can be combined in various ways to store larger
amounts of data.
The function generators (LUTs) in SLICEM can be implemented as a 16 x 1-bit synchronous
RAM resource called a distributed RAM element. RAM elements are configurable within a
CLB to implement the following:
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Distributed RAM modules are synchronous (write) resources. A synchronous read can be
implemented with a storage element in the same slice. The distributed RAM and the
No set or reset
Synchronous set
Synchronous reset
Synchronous set and reset
Asynchronous set (preset)
Asynchronous reset (clear)
Asynchronous set and reset (preset and clear)
Single-Port 16 x 4-bit RAM
Single-Port 32 x 2-bit RAM
Single-Port 64 x 1-bit RAM
Dual-Port 16 x 2-bit RAM
CLK
Figure 5-4: Register/Latch Configuration in a Slice
CE
SR
BY
BX
LUT F Output
www.xilinx.com
LUT G Output
D
CE
CK
D
CE
CK
SR REV
SR REV
FFY
FFX
FF
LATCH
FF
LATCH
Q
Q
UG070 (v2.6) December 1, 2008
Attribute
Attribute
ug070_5_04_071504
Reset Type
Virtex-4 FPGA User Guide
INIT1
INIT0
SRHIGH
SRLOW
INIT1
INIT0
SRHIGH
SRLOW
SYNC
ASYNC
YQ
XQ
R