XC4VFX20-10FFG672C Xilinx Inc, XC4VFX20-10FFG672C Datasheet - Page 189
XC4VFX20-10FFG672C
Manufacturer Part Number
XC4VFX20-10FFG672C
Description
IC FPGA VIRTEX-4 FX 20K 672-FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-4r
Datasheets
1.XC4VFX12-10FFG668C.pdf
(58 pages)
2.XC4VFX12-10FFG668C.pdf
(9 pages)
3.XC4VFX12-10FFG668C.pdf
(406 pages)
Specifications of XC4VFX20-10FFG672C
Total Ram Bits
1253376
Number Of Logic Elements/cells
19224
Number Of Labs/clbs
2136
Number Of I /o
320
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-BBGA, FCBGA
No. Of Logic Blocks
19224
No. Of Macrocells
19224
No. Of Speed Grades
10
No. Of I/o's
320
Clock Management
DCM
I/o Supply Voltage
3.45V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
HW-V4-ML405-UNI-G - EVALUATION PLATFORM VIRTEX-4
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
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Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
R
storage element share the same clock input. For a write operation, the Write Enable (WE)
input, driven by the SR pin, must be set High.
Table 5-3
configuration.
Table 5-3: Distributed RAM Configuration
For single-port configurations, distributed RAM has a common address port for
synchronous writes and asynchronous reads.
For dual-port configurations, distributed RAM has one port for synchronous writes and
asynchronous reads and another port for asynchronous reads. The function generator
(LUT) has separated read address inputs and write address inputs.
In single-port mode, read and write addresses share the same address bus. In dual-port
mode, one function generator (R/W port) is connected with shared read and write
addresses. The second function generator has the A inputs (Read) connected to the second
read-only port address and the W inputs (Write) shared with the first read/write port
address.
Figure
configurations occupying one slice.
Notes:
1. S = single-port configuration; D = dual-port configuration
5-5,
shows the number of LUTs (two per slice) occupied by each distributed RAM
16 x 1D
16 x 1S
32 x 1S
64 x 1S
Figure
RAM
5-6, and
WCLK
A[3:0]
WE
Figure 5-5: Distributed RAM (RAM16x1S)
D
www.xilinx.com
Figure 5-7
4
(BY)
(SR)
4
RAM 16x1S
WE
CK
A[4:1]
WG[4:1]
WSG
WS
Number of LUTs
RAM
illustrate various example distributed RAM
DI
1
2
2
4
D
(optional)
D
Q
ug070_5_05_071504
Output
Registered
Output
CLB Overview
189
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