XC4VFX20-10FFG672C Xilinx Inc, XC4VFX20-10FFG672C Datasheet - Page 45

• Manufacturer Part Number: XC4VFX20-10FFG672C
• Description: IC FPGA VIRTEX-4 FX 20K 672-FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX20-10FFG672C

• Total Ram Bits: 1253376
• Number Of Logic Elements/cells: 19224
• Number Of Labs/clbs: 2136
• Number Of I /o: 320
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-BBGA, FCBGA
• No. Of Logic Blocks: 19224
• No. Of Macrocells: 19224
• No. Of Speed Grades: 10
• No. Of I/o's: 320
• Clock Management: DCM
• I/o Supply Voltage: 3.45V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V4-ML405-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

VHDL and Verilog Templates
Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
Regional Clock Nets
BUFGCTRL VHDL and Verilog Templates
R
VHDL Template
In addition to global clock trees and nets, Virtex-4 devices contain regional clock nets.
These clock trees are also designed for low-skew and low-power operation. Unused
branches are disconnected. The clock trees also manage the load/fanout when all the logic
resources are used.
Regional clock nets do not propagate throughout the whole Virtex-4 device. Instead, they
are limited to only one clock region. One clock region contains two independent regional
clock nets.
To access regional clock nets, BUFRs must be instantiated. A BUFR can drive regional
clocks in up to two adjacent clock regions
can only access one adjacent region; below or above respectively.
The VHDL and Verilog code follows for all clocking resource primitives.
The following examples illustrate the instantiation of the BUFGCTRL module in VHDL
and Verilog.
BUFRs
--Example BUFGCTRL declaration
component BUFGCTRL
generic(
INIT_OUT
Figure 1-23: BUFR Driving Multiple Regions
www.xilinx.com
: integer := 0;
(Figure
1-23). BUFRs in the top or bottom region
VHDL and Verilog Templates
ug070_1_23_071404
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