XC4VFX20-10FFG672C Xilinx Inc, XC4VFX20-10FFG672C Datasheet - Page 325
XC4VFX20-10FFG672C
Manufacturer Part Number
XC4VFX20-10FFG672C
Description
IC FPGA VIRTEX-4 FX 20K 672-FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-4r
Datasheets
1.XC4VFX12-10FFG668C.pdf
(58 pages)
2.XC4VFX12-10FFG668C.pdf
(9 pages)
3.XC4VFX12-10FFG668C.pdf
(406 pages)
Specifications of XC4VFX20-10FFG672C
Total Ram Bits
1253376
Number Of Logic Elements/cells
19224
Number Of Labs/clbs
2136
Number Of I /o
320
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-BBGA, FCBGA
No. Of Logic Blocks
19224
No. Of Macrocells
19224
No. Of Speed Grades
10
No. Of I/o's
320
Clock Management
DCM
I/o Supply Voltage
3.45V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
HW-V4-ML405-UNI-G - EVALUATION PLATFORM VIRTEX-4
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
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Quantity
Price
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Part Number:
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Part Number:
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Manufacturer:
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Quantity:
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Company:
Part Number:
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Manufacturer:
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Quantity:
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Quantity:
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- XC4VFX12-10FFG668C PDF datasheet
- XC4VFX12-10FFG668C PDF datasheet #2
- XC4VFX12-10FFG668C PDF datasheet #3
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- Download datasheet (6Mb)
Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
CE
Q1
Q2
C
D
R
D0A
Don't care
SAME_EDGE Mode
D1A
In the SAME_EDGE mode a third register (IFF4), clocked by the rising edge clock, is placed
on the output of the falling edge register.
signals associated with the SAME_EDGE mode.
By adding the third register, data is presented into the FPGA fabric on the same clock edge.
However, the additional register causes the data pair to be separated by one clock cycle.
Figure 7-5
the timing diagram, the output pairs are no longer (0) and (1). Instead, the first pair
presented is pair (0) and (don't care), followed by pair (1) and (2) on the next clock cycle.
D0A
D2A
Figure 7-5: Input DDR Timing in SAME_EDGE Mode
CE
D
R
D3A
shows the timing diagram of the input DDR using the SAME_EDGE mode. In
C
S
D2A
D1A
D4A
Figure 7-4: Input DDR in SAME_EDGE Mode
D5A
www.xilinx.com
D4A
D3A
D6A
D
R
CE
D
R
CE
CLK
CLK
D7A
D6A
D5A
S
S
Figure 7-4
D8A
Q
Q
D9A
shows input DDR registers and the
D8A
D7A
D10A
D
R
CE
CLK
D11A
S
D10A
D9A
Q
ug070_7_04_071404
ILOGIC Resources
ug070_7_05_072904
Q1
Q2
D11A
325
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