XC4VFX20-10FFG672C Xilinx Inc, XC4VFX20-10FFG672C Datasheet - Page 281

• Manufacturer Part Number: XC4VFX20-10FFG672C
• Description: IC FPGA VIRTEX-4 FX 20K 672-FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX20-10FFG672C

• Total Ram Bits: 1253376
• Number Of Logic Elements/cells: 19224
• Number Of Labs/clbs: 2136
• Number Of I /o: 320
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-BBGA, FCBGA
• No. Of Logic Blocks: 19224
• No. Of Macrocells: 19224
• No. Of Speed Grades: 10
• No. Of I/o's: 320
• Clock Management: DCM
• I/o Supply Voltage: 3.45V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V4-ML405-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
SSTL (Stub-Series Terminated Logic)
R
SSTL2_I, SSTL18_I Usage
SSTL2_I_DCI, SSTL18_I_DCI Usage
SSTL2_II, SSTL18_II Usage
SSTL2_II_DCI, SSTL18_II_DCI Usage
Table 6-24
Table 6-24: Allowed Attributes of the HSTL I/O Standards
Table 6-25
standards.
Table 6-25: Allowed Attributes of the DIFF_HSTL I/O Standards
The Stub-Series Terminated Logic (SSTL) for 2.5V (SSTL2) and 1.8V (SSTL18) is a standard
for a general purpose memory bus. These standards are sponsored by Hitachi, IBM, and
are defined in the JEDEC JESD8-15 documents. The standard has two classes; Class I is for
unidirectional and Class II is for bidirectional signaling. Virtex-4 FPGA I/O supports both
standards for single-ended signaling and Class II only for differential signaling. This
standard requires a differential amplifier input buffer and a push-pull output buffer.
Class I signaling uses V
the receiver. A series resistor (25Ω at 2.5V, 20Ω at 1.8V) must be connected to the
transmitter output.
The DCI transmitter provides the internal series resistance (25Ω at 2.5V, 20Ω at 1.8V). The
DCI receiver has an internal split thevenin termination powered from V
equivalent V
Class II signaling uses V
the receiver and transmitter respectively. A series resistor (25Ω at 2.5V, 20Ω at 1.8V) must
be connected to the transmitter output for a unidirectional link. For a bidirectional link,
25Ω series resistors must connected the transmitters of the transceivers.
The DCI circuits have a split thevenin termination powered from V
series resistor (25Ω at 2.5V, 20Ω at 1.8V). For a unidirectional link the series resistance is
supplied only for the transmitter. A bidirectional link has the series resistor for both
transmitters.
IOSTANDARD
CAPACITANCE
IOSTANDARD
CAPACITANCE
Attributes
Attributes
details the allowed attributes that can be applied to the HSTL I/O standards.
details the allowed attributes that can be applied to the DIFF_HSTL I/O
TT
voltage and termination impedance.
Specific Guidelines for Virtex-4 FPGA I/O Supported Standards
TT
TT
www.xilinx.com
IBUFDS/IBUFGDS
(V
(V
CCO
CCO
IBUF/IBUFG
/2) as a parallel termination voltage to a 50Ω resistor at
/2) as a parallel termination voltage to a 50Ω resistor at
All possible DIFF_HSTL standards
LOW, NORMAL, DONT_CARE
LOW, NORMAL, DONT_CARE
All possible HSTL standards
OBUFDS/OBUFTDS
OBUF/OBUFT
Primitives
Primitives
CCO
CCO
and an internal
IOBUFDS
IOBUF
creating an
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