XC4VFX20-10FFG672C Xilinx Inc, XC4VFX20-10FFG672C Datasheet - Page 173
XC4VFX20-10FFG672C
Manufacturer Part Number
XC4VFX20-10FFG672C
Description
IC FPGA VIRTEX-4 FX 20K 672-FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-4r
Datasheets
1.XC4VFX12-10FFG668C.pdf
(58 pages)
2.XC4VFX12-10FFG668C.pdf
(9 pages)
3.XC4VFX12-10FFG668C.pdf
(406 pages)
Specifications of XC4VFX20-10FFG672C
Total Ram Bits
1253376
Number Of Logic Elements/cells
19224
Number Of Labs/clbs
2136
Number Of I /o
320
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-BBGA, FCBGA
No. Of Logic Blocks
19224
No. Of Macrocells
19224
No. Of Speed Grades
10
No. Of I/o's
320
Clock Management
DCM
I/o Supply Voltage
3.45V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
HW-V4-ML405-UNI-G - EVALUATION PLATFORM VIRTEX-4
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
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Manufacturer
Quantity
Price
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Part Number:
XC4VFX20-10FFG672C
Manufacturer:
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Quantity:
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Company:
Part Number:
XC4VFX20-10FFG672C
Manufacturer:
Xilinx Inc
Quantity:
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Part Number:
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Manufacturer:
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Quantity:
20 000
- XC4VFX12-10FFG668C PDF datasheet
- XC4VFX12-10FFG668C PDF datasheet #2
- XC4VFX12-10FFG668C PDF datasheet #3
- Current page: 173 of 406
- Download datasheet (6Mb)
Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
R
Resource Utilization
Performance
Design Files
The resources used in implementing the solution described above with a 400 MHz
FASTCLK are as follows.
The design was implemented using the ISE 8.1i software with default settings for MAP,
Place, and Route. The approximate resource count was 20 LUTs and 24 flip-flops per FIFO.
One DCM is required to generate a 400 MHz clock if a 200 MHz input clock is available.
Two DCMs are needed if only a 100 MHz input clock is available. One extra BUFG was
used per device.
The maximum FASTCLK frequency for each speed grade is Global Clock Tree FMAX, as
given in the
RDCLK and WRCLK frequency is 1/3 the FASTCLK frequency. If the system design
guarantees that there is at least one clock cycle between all reads and all writes, then the
maximum RDCLK and WRCLK frequency is 2/3 the FASTCLK frequency. If the system
design guarantees that there are at least two clock cycles between all reads and all writes,
then the RDCLK and WRCLK frequency can be equal to the FASTCLK frequency.
All the necessary files required for the above design are contained in a ZIP archive
downloadable from the Xilinx website at:
Open the ZIP archive and extract FIFO16_solution2.zip.
https://secure.xilinx.com/webreg/clickthrough.do?cid=30163
Virtex-4 Data
Sheet. If any back-to-back reads or writes occur, the maximum
www.xilinx.com
FIFO16 Error Condition and Work-Arounds
173
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