XC4VFX20-10FFG672C Xilinx Inc, XC4VFX20-10FFG672C Datasheet - Page 33

• Manufacturer Part Number: XC4VFX20-10FFG672C
• Description: IC FPGA VIRTEX-4 FX 20K 672-FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX20-10FFG672C

• Total Ram Bits: 1253376
• Number Of Logic Elements/cells: 19224
• Number Of Labs/clbs: 2136
• Number Of I /o: 320
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-BBGA, FCBGA
• No. Of Logic Blocks: 19224
• No. Of Macrocells: 19224
• No. Of Speed Grades: 10
• No. Of I/o's: 320
• Clock Management: DCM
• I/o Supply Voltage: 3.45V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V4-ML405-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
R
Figure 1-7
BUFGMUX and BUFGMUX_1
BUFGMUX is a clock buffer with two clock inputs, one clock output, and a select line. This
primitive is based on BUFGCTRL with some pins connected to logic High or Low.
Figure 1-8
available for BUFGMUX and BUFGCTRL.
Since the BUFGMUX uses the CE pins as select pins, when using the select, the setup time
requirement must be met. Violating this setup time may result in a glitch.
Switching conditions for BUFGMUX are the same as the CE pins on BUFGCTRL.
Figure 1-9
BUFGCE_1(CE)
BUFGCE_1(O)
illustrates the timing diagram for BUFGCE_1.
illustrates the relationship of BUFGMUX and BUFGCTRL. A LOC constraint is
illustrates the timing diagram for BUFGMUX.
BUFGCE_1(I)
I1
I0
S
I 0
I1
O
S
BUFGMUX
Figure 1-7: BUFGCE_1 Timing Diagram
Figure 1-9: BUFGMUX Timing Diagram
Figure 1-8: BUFGMUX as BUFGCTRL
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T
BCCKO_O
O
i hi
T
S
BCCKO_O
begin
i
T
BCCCK_CE
I1
GND
GND
V
V
DD
DD
T
BCCCK_CE
IGNORE1
CE1
S1
I1
I0
S0
CE0
IGNORE0
T
Global Clocking Resources
BCCKO_O
ug070_1_08_071304
ug070_1_07_081904
O
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