XC4VFX20-10FFG672C Xilinx Inc, XC4VFX20-10FFG672C Datasheet - Page 156

• Manufacturer Part Number: XC4VFX20-10FFG672C
• Description: IC FPGA VIRTEX-4 FX 20K 672-FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX20-10FFG672C

• Total Ram Bits: 1253376
• Number Of Logic Elements/cells: 19224
• Number Of Labs/clbs: 2136
• Number Of I /o: 320
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-BBGA, FCBGA
• No. Of Logic Blocks: 19224
• No. Of Macrocells: 19224
• No. Of Speed Grades: 10
• No. Of I/o's: 320
• Clock Management: DCM
• I/o Supply Voltage: 3.45V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V4-ML405-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Chapter 4: Block RAM
FIFO Timing Models and Parameters
Table 4-14: FIFO Timing Parameters
156
Setup and Hold Relative to Clock (CLK)
T
T
T
T
T
T
T
T
Sequential Delays
T
T
T
T
T
T
T
T
T
Reset to Out
T
T
T
FXCK
FCKX
FDCK_DI
FCKD_DI
FCCK_RDEN
FCKC_RDEN
FCCK_WREN
FCKC_WREN
FCKO_DO
FCKO_AEMPTY
FCKO_AFULL
FCKO_EMPTY
FCKO_FULL
FCKO_RDERR
FCKO_WRERR
FCKO_RDCOUNT
FCKO_WRCOUNT
FCO_AEMPTY
FCO_AFULL
FCO_EMPTY
Parameter
= Setup time (before clock edge)
= Hold time (after clock edge)
/
(4)
(1)
(2)
/
(5)
/
(5)
(2)
(2)
(2)
(2)
(2)
(3)
(3)
Data inputs
Read enable
Write enable
Clock to data output
Clock to ALMOSTEMPTY
output
Clock to ALMOSTFULL
output
Clock to EMPTY output
Clock to FULL output
Clock to read error output
Clock to write error
output
Clock to read pointer
output
Clock to write pointer
output
Reset to ALMOSTEMPTY
output
Reset to ALMOSTFULL
output
Reset to EMPTY output
Table 4-14
Function
shows the FIFO parameters.
The following descriptions are for setup times only.
WRCOUNT
RDCOUNT
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AEMPTY
AEMPTY
Control
WRERR
EMPTY
RDERR
EMPTY
AFULL
AFULL
WREN
Signal
RDEN
FULL
DO
DI
Time before WRCLK that data must be stable at the
DI inputs of the FIFO.
Time before RDCLK that Read Enable must be stable
at the RDEN inputs of the FIFO.
Time before WRCLK that write enable must be
stable at the WREN inputs of the FIFO.
Time after RDCLK that the output data is stable at
the DO outputs of the FIFO.
Time after RDCLK that the ALMOSTEMPTY signal
is stable at the ALMOSTEMPTY outputs of the FIFO.
Time after WRCLK that the ALMOSTFULL signal is
stable at the ALMOSTFULL outputs of the FIFO.
Time after RDCLK that the Empty signal is stable at
the EMPTY outputs of the FIFO.
Time after WRCLK that the FULL signal is stable at
the FULL outputs of the FIFO.
Time after RDCLK that the Read Error signal is
stable at the RDERR outputs of the FIFO.
Time after WRCLK that the Write Error signal is
stable at the WRERR outputs of the FIFO.
Time after RDCLK that the Read pointer signal is
stable at the RDCOUNT outputs of the FIFO.
Time after WRCLK that the Write pointer signal is
stable at the WRCOUNT outputs of the FIFO.
Time after reset that the ALMOSTEMPTY signal is
stable at the ALMOSTEMPTY outputs of the FIFO.
Time after reset that the ALMOSTFULL signal is
stable at the ALMOSTFULL outputs of the FIFO.
Time after reset that the Empty signal is stable at the
EMPTY outputs of the FIFO.
Description
UG070 (v2.6) December 1, 2008
Virtex-4 FPGA User Guide
R