XC4VFX20-10FFG672C Xilinx Inc, XC4VFX20-10FFG672C Datasheet - Page 181

IC FPGA VIRTEX-4 FX 20K 672-FBGA

XC4VFX20-10FFG672C

Manufacturer Part Number
XC4VFX20-10FFG672C
Description
IC FPGA VIRTEX-4 FX 20K 672-FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-4r

Specifications of XC4VFX20-10FFG672C

Total Ram Bits
1253376
Number Of Logic Elements/cells
19224
Number Of Labs/clbs
2136
Number Of I /o
320
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-BBGA, FCBGA
No. Of Logic Blocks
19224
No. Of Macrocells
19224
No. Of Speed Grades
10
No. Of I/o's
320
Clock Management
DCM
I/o Supply Voltage
3.45V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
HW-V4-ML405-UNI-G - EVALUATION PLATFORM VIRTEX-4
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

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0
Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
R
Block RAM ECC Verilog Template
RAMB32_S64_ECC Verilog:
// RAMB32_S64_ECC: To incorporate this function into the design,
//
//
//
//
//
//
//
RAMB32_S64_ECC_inst: RAMB32_S64_ECC_inst (
generic map (
-- End of RAMB32_S64_ECC_inst instantiation
// RAMB32_S64_ECC: Virtex-4 512 x 64 Error Correction Block RAM
// Virtex-4 FPGA User Guide
RAMB32_S64_ECC #(
);
// End of RAMB32_S64_ECC_inst instantiation
declaration
<-----Cut code below this line---->
) RAMB32_S64_ECC_inst (
instance
Verilog
DO_REG => 0, -- Optional output registers (0 or 1)
port map (
);
.DO_REG(0),
.DO(DO),
.STATUS(STATUS), // 2-bit status output
.DI(DI),
.RDADDR(RDADDR), // 9-bit data address input
.RDCLK(RDCLK),
.RDEN(RDEN),
.SSR(SSR),
.WRADDR(WRADDR), // 9-bit write address input
.WRCLK(WRCLK),
.WREN(WREN)
code
DO => DO,
STATUS => STATUS, -- 2-bit status output
DI => DI,
RDADDR => RDADDR, -- 9-bit data address input
RDCLK => RDCLK,
RDEN => RDEN,
SSR => SSR,
WRADDR =>WRADDR,
WRCLK => WRCLK,
WREN => WREN
: the following instance declaration needs to be placed
: in the body of the design code. The instance name
: (RAMB32_S64_ECC_inst) and/or the port declarations
: within the parenthesis can be changed to properly
: reference and connect this function to the design.
: All inputs and outputs must be connected.
www.xilinx.com
// Optional output registers (0 or 1)
// 64-bit output data
// 64-bit data input
// 1-bit read clock input
// 1-bit read enable input
// 1-bit synchronous reset
// 1-bit write clock input
// 1-bit write enable input
-- 64-bit output data
-- 64-bit data input
-- 1-bit read clock input
-- 1-bit read enable input
-- 1-bit synchronous reset
-- 9-bit write address input
-- 1-bit write clock input
-- 1-bit write enable input
Built-in Block RAM Error Correction Code
181

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