D12363VTE33 Renesas Electronics America, D12363VTE33 Datasheet - Page 181

MCU 3V 0K 120-TQFP

D12363VTE33

Manufacturer Part Number
D12363VTE33
Description
MCU 3V 0K 120-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet

Specifications of D12363VTE33

Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
84
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
120-TQFP, 120-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Other names
HD6412363VTE33
HD6412363VTE33

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
D12363VTE33V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
6.2
Table 6.1 summarizes the pin configuration of the bus controller.
Table 6.1
Name
Address strobe
Read
High write
Low write
Chip select 0
Chip select 1
Chip select 2/row address
strobe 2
Chip select 3/row address
strobe 3
Chip select 4
Chip select 5
Chip select 6
Chip select 7
Upper column address strobe
Input/Output Pins
Pin Configuration
Symbol
AS
RD
HWR
LWR
CS0
CS1
CS2/
RAS2
CS3/
RAS3
CS4
CS5
CS6
CS7
UCAS
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
I/O
Function
Strobe signal indicating that normal space
is accessed and address output on
address bus is enabled.
Strobe signal indicating that normal space
is being read.
Strobe signal indicating that normal space
is written to, and upper half (D15 to D8) of
data bus is enabled or DRAM space write
enable signal.
Strobe signal indicating that normal space
is written to, and lower half (D7 to D0) of
data bus is enabled.
Strobe signal indicating that area 0 is
selected.
Strobe signal indicating that area 1 is
selected
Strobe signal indicating that area 2 is
selected, DRAM row address strobe signal
when area 2 is DRAM space or areas 2 to
5 are set as continuous DRAM space.
Strobe signal indicating that area 3 is
selected, DRAM row address strobe signal
when area 3 is DRAM space.
Strobe signal indicating that area 4 is
selected.
Strobe signal indicating that area 5 is
selected.
Strobe signal indicating that area 6 is
selected.
Strobe signal indicating that area 7 is
selected.
16-bit DRAM space upper column address
strobe signal, 8-bit DRAM space column
address strobe signal.
Rev.6.00 Mar. 18, 2009 Page 121 of 980
Section 6 Bus Controller (BSC)
REJ09B0050-0600

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