D12363VTE33 Renesas Electronics America, D12363VTE33 Datasheet - Page 667

• Manufacturer Part Number: D12363VTE33
• Description: MCU 3V 0K 120-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of D12363VTE33

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 84
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412363VTE33; HD6412363VTE33

asynchronous mode) as determined by bits BCP1 and BCP0. In reception, the SCI samples the
falling edge of the start bit using the basic clock, and performs internal synchronization. As
shown in figure 14.25, by sampling receive data at the rising-edge of the 16th, 32nd, 186th, or
128th pulse of the basic clock, data can be latched at the middle of the bit. The reception margin is
given by the following formula.
M = | (0.5 –
Where M: Reception margin (%)
Assuming values of F = 0, D = 0.5 and N = 372 in the above formula, the reception margin
formula is as follows.
M = (0.5 – 1/2 × 372) × 100%
= 49.866%
Internal
basic clock
Receive data
(RxD)
Synchronization
sampling timing
Data sampling
timing
N: Ratio of bit rate to clock (N = 32, 64, 372, and 256)
D: Clock duty (D = 0 to 1.0)
L: Frame length (L = 10)
F: Absolute value of clock frequency deviation
Figure 14.25 Receive Data Sampling Timing in Smart Card Mode
2N
1
) – (L – 0.5) F –
186 clocks
0
(Using Clock of 372 Times the Bit Rate)
185
372 clocks
Start bit
| D – 0.5 |
N
Section 14 Serial Communication Interface (SCI, IrDA)
371
0
(1 + F) |
D0
Rev.6.00 Mar. 18, 2009 Page 607 of 980
100%
185
371 0
REJ09B0050-0600
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