D12363VTE33 Renesas Electronics America, D12363VTE33 Datasheet - Page 718

• Manufacturer Part Number: D12363VTE33
• Description: MCU 3V 0K 120-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of D12363VTE33

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 84
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412363VTE33; HD6412363VTE33

Section 15 I
15.5
There are six interrupt requests in this module; transmit data empty, transmit end, receive data full,
NACK receive, STOP recognition, and arbitration lost. Table 15.3 shows the contents of each
interrupt request.
Table 15.3 Interrupt Requests
Interrupt Request
Transmit Data Empty
Transmit End
Receive Data Full
STOP Recognition
NACK Detection
Arbitration Lost
When interrupt conditions described in table 15.3 are 1 and the CPU is ready to receive interrupts,
an interrupt execution handling is executed. Clear each interrupt source during an interrupt
execution handling. Note that TDRE and TEND are automatically cleared by writing the transmit
data to ICDRT, and RDRF is automatically cleared by reading ICDRR. When the transmit data is
written to ICDRT, TDRE is set again simultaneously. When TDRE is cleared, extra one byte of
data may be transmitted.
15.6
In master mode,
• When SCL is driven to low by the slave device
• When the rising speed of SCL is lower by the load of the SCL line (load capacitance or pull-up
This module has a possibility that high level period may be short in the two states described
above. Therefore it monitors SCL and communicates by bit with synchronization.
Figure 15.18 shows the timing of the bit synchronous circuit and table 15.4 shows the time when
SCL output changes from low to Hi-Z then SCL is monitored.
Rev.6.00 Mar. 18, 2009 Page 658 of 980
REJ09B0050-0600
resistance)
Interrupt Request
Bit Synchronous Circuit
2
C Bus Interface2 (IIC2) (Option)
Abbreviation
TXI
TEI
RXI
STPI
NAKI
Interrupt Condition
(TDRE = 1)
(TEND = 1)
(RDRF = 1)
(STOP = 1)
{(NACKF = 1)+(AL = 1)}
•
•
•
•
(STIE = 1)
(TIE = 1)
(TEIE = 1)
(RIE = 1)
•
(NAKIE = 1)