D12363VTE33 Renesas Electronics America, D12363VTE33 Datasheet - Page 25

• Manufacturer Part Number: D12363VTE33
• Description: MCU 3V 0K 120-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of D12363VTE33

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 84
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412363VTE33; HD6412363VTE33

5.4
5.5
5.6
5.7
Section 6 Bus Controller (BSC)
6.1
6.2
6.3
5.3.3
5.3.4
5.3.5
5.3.6
5.3.7
Interrupt Sources ............................................................................................................... 101
5.4.1
5.4.2
Interrupt Exception Handling Vector Table...................................................................... 103
Interrupt Control Modes and Interrupt Operation ............................................................. 108
5.6.1
5.6.2
5.6.3
5.6.4
5.6.5
Usage Notes ...................................................................................................................... 116
5.7.1
5.7.2
5.7.3
5.7.4
5.7.5
5.7.6
Features ............................................................................................................................. 119
Input/Output Pins .............................................................................................................. 121
Register Descriptions ........................................................................................................ 122
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.3.6
6.3.7
6.3.8
6.3.9
6.3.10 Refresh Control Register (REFCR) ..................................................................... 141
6.3.11 Refresh Timer Counter (RTCNT)........................................................................ 144
IRQ Enable Register (IER) .................................................................................. 95
IRQ Sense Control Register L (ISCRL)............................................................... 96
IRQ Status Register (ISR).................................................................................... 99
IRQ Pin Select Register (ITSR) ........................................................................... 100
Software Standby Release IRQ Enable Register (SSIER) ................................... 101
External Interrupts ............................................................................................... 101
Internal Interrupts................................................................................................. 102
Interrupt Control Mode 0 ..................................................................................... 108
Interrupt Control Mode 2 ..................................................................................... 110
Interrupt Exception Handling Sequence .............................................................. 112
Interrupt Response Times .................................................................................... 114
DTC and DMAC Activation by Interrupt ............................................................ 115
Contention between Interrupt Generation and Disabling..................................... 116
Instructions that Disable Interrupts ...................................................................... 117
Times when Interrupts Are Disabled ................................................................... 117
Interrupts during Execution of EEPMOV Instruction.......................................... 117
Change of IRQ Pin Select Register (ITSR) Setting ............................................. 117
Note on IRQ Status Register (ISR) ...................................................................... 118
Bus Width Control Register (ABWCR)............................................................... 123
Access State Control Register (ASTCR) ............................................................. 123
Wait Control Registers AH, AL, BH, and BL (WTCRAH, WTCRAL,
WTCRBH, and WTCRBL).................................................................................. 124
Read Strobe Timing Control Register (RDNCR)................................................. 129
CS Assertion Period Control Registers H, L (CSACRH, CSACRL)................... 130
Area 0 Burst ROM Interface Control Register (BROMCRH) Area 1
Burst ROM Interface Control Register (BROMCRL) ......................................... 132
Bus Control Register (BCR) ................................................................................ 133
DRAM Control Register (DRAMCR) ................................................................. 135
DRAM Access Control Register (DRACCR)...................................................... 140
...................................................................................... 119
Rev.6.00 Mar. 18, 2009 Page xxiii of lviii
REJ09B0050-0600