D12363VTE33 Renesas Electronics America, D12363VTE33 Datasheet - Page 189

• Manufacturer Part Number: D12363VTE33
• Description: MCU 3V 0K 120-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of D12363VTE33

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 84
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412363VTE33; HD6412363VTE33

6.3.4
RDNCR selects the read strobe signal (RD) negation timing in a basic bus interface read access.
Bit
7
6
5
4
3
2
1
0
RDNn = 0
RDNn = 1
Bit Name
RDN7
RDN6
RDN5
RDN4
RDN3
RDN2
RDN1
RDN0
Figure 6.2 Read Strobe Negation Timing (Example of 3-State Access Space)
Read Strobe Timing Control Register (RDNCR)
RD
Data
RD
Data
φ
Initial Value
0
0
0
0
0
0
0
0
T
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Read Strobe Timing Control 7 to 0
These bits set the negation timing of the read
strobe in a corresponding area read access.
As shown in figure 6.2, the read strobe for an
area for which the RDNn bit is set to 1 is
negated one half-state earlier than that for an
area for which the RDNn bit is cleared to 0. The
read data setup and hold time specifications are
also one half-state earlier.
0: In an area n read access, the RD is negated
1: In an area n read access, the RD is negated
at the end of the read cycle
one half-state before the end of the read cycle
Bus cycle
T
Rev.6.00 Mar. 18, 2009 Page 129 of 980
2
Section 6 Bus Controller (BSC)
T
3
REJ09B0050-0600
(n = 7 to 0)