D12363VTE33 Renesas Electronics America, D12363VTE33 Datasheet - Page 27

• Manufacturer Part Number: D12363VTE33
• Description: MCU 3V 0K 120-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of D12363VTE33

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 84
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412363VTE33; HD6412363VTE33

6.12 Bus Controller Operation in Reset .................................................................................... 211
6.13 Usage Notes ...................................................................................................................... 211
Section 7 DMA Controller (DMAC)
7.1
7.2
7.3
7.4
7.5
6.11.1 Operation ............................................................................................................. 209
6.11.2 Bus Transfer Timing ............................................................................................ 210
6.13.1 External Bus Release Function and All-Module-Clocks-Stopped Mode............. 211
6.13.2 External Bus Release Function and Software Standby ........................................ 211
6.13.3 External Bus Release Function and CBR Refreshing .......................................... 211
6.13.4 BREQO Output Timing ....................................................................................... 212
Features ............................................................................................................................. 213
Input/Output Pins .............................................................................................................. 215
Register Descriptions ........................................................................................................ 215
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
7.3.6
7.3.7
Activation Sources ............................................................................................................ 241
7.4.1
7.4.2
7.4.3
Operation........................................................................................................................... 244
7.5.1
7.5.2
7.5.3
7.5.4
7.5.5
7.5.6
7.5.7
7.5.8
7.5.9
7.5.10 DMA Transfer (Single Address Mode) Bus Cycles............................................. 275
7.5.11 Write Data Buffer Function ................................................................................. 281
7.5.12 Multi-Channel Operation ..................................................................................... 282
7.5.13 Relation between DMAC and External Bus Requests and Refresh Cycles ......... 283
7.5.14 DMAC and NMI Interrupts.................................................................................. 284
7.5.15 Forced Termination of DMAC Operation............................................................ 285
Memory Address Registers (MARA and MARB) ............................................... 217
I/O Address Registers (IOARA and IOARB) ...................................................... 217
Execute Transfer Count Registers (ETCRA and ETCRB)................................... 218
DMA Control Registers (DMACRA and DMACRB) ......................................... 219
DMA Band Control Registers H and L (DMABCRH and DMABCRL)............. 226
DMA Write Enable Register (DMAWER) .......................................................... 238
DMA Terminal Control Register (DMATCR)..................................................... 240
Activation by Internal Interrupt Request.............................................................. 242
Activation by External Request ........................................................................... 242
Activation by Auto-Request................................................................................. 243
Transfer Modes .................................................................................................... 244
Sequential Mode .................................................................................................. 246
Idle Mode............................................................................................................. 249
Repeat Mode ........................................................................................................ 252
Single Address Mode ........................................................................................... 256
Normal Mode ....................................................................................................... 259
Block Transfer Mode ........................................................................................... 262
Basic Bus Cycles.................................................................................................. 267
DMA Transfer (Dual Address Mode) Bus Cycles ............................................... 267
............................................................................. 213
Rev.6.00 Mar. 18, 2009 Page xxv of lviii
REJ09B0050-0600