D12363VTE33 Renesas Electronics America, D12363VTE33 Datasheet - Page 455

• Manufacturer Part Number: D12363VTE33
• Description: MCU 3V 0K 120-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of D12363VTE33

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 84
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412363VTE33; HD6412363VTE33

9.14
Port G is a 7-bit I/O port that also has other functions. The port G has the following registers.
• Port G data direction register (PGDDR)
• Port G data register (PGDR)
• Port G register (PORTG)
• Port Function Control Register 0 (PFCR0)
9.14.1
The individual bits of PGDDR specify input or output for the pins of port G.
PGDDR cannot be read; if it is, an undefined value will be read.
Note:
Bit
7
6
5
4
3
2
1
0
*
Bit Name
—
PG6DDR
PG5DDR
PG4DDR
PG3DDR
PG2DDR
PG1DDR
PG0DDR
Port G
Port G Data Direction Register (PGDDR)
PG0DDR is initialized to 1 in modes 1 and 2, and to 0 in modes 4 and 7.
Initial Value
0
0
0
0
0
0
0
1/0 *
R/W
—
W
W
W
W
W
W
W
Description
Reserved
•
Pins PG6 and PG5 function as bus control
input/output pins (BREQ and BACK) when the
appropriate bus controller settings are made.
Otherwise, these pins are I/O ports, and their
functions can be switched with PGDDR. Pin PG4
functions as the bus control input/output pin
(BREQO) when the appropriate bus controller
settings are made. Otherwise, when the CS7E bit is
set to 1, pin PG4 functions as the CS7 output pin
when PG4DDR is set to 1, and as an input port
when the bit is cleared to 0. When the CS7E bit is
cleared to 0, pin PG4 is an I/O port, and its function
can be switched with PG4DDR. When the CS
output enable bits (CS3E to CS0E) are set to 1, pins
PG3 to PG0 function as CS output pins when the
corresponding PGDDR bit is set to 1, and as input
ports when the bit is cleared to 0. When CS3E to
CS0E are cleared to 0, pins PG3 to PG0 are I/O
ports, and their functions can be switched with
PGDDR.
•
Pins PG6 to PG0 are I/O ports, and their functions
can be switched with PGDDR.
Modes 1, 2, 4, and 7 (when EXPE = 1)
Mode 7 (when EXPE = 0)
Rev.6.00 Mar. 18, 2009 Page 395 of 980
Section 9 I/O Ports
REJ09B0050-0600