D12363VTE33 Renesas Electronics America, D12363VTE33 Datasheet - Page 279

• Manufacturer Part Number: D12363VTE33
• Description: MCU 3V 0K 120-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of D12363VTE33

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 84
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412363VTE33; HD6412363VTE33

7.3.4
DMACR controls the operation of each DMAC channel.
The DMA has four DMACR registers: DMACR_0A in channel 0 (channel 0A), DMACR_0B in
channel 0 (channel 0B), DMACR_1A in channel 1 (channel 1A), and DMACR_1B in channel 1
(channel 1B).
In short address mode, channels A and B operate independently, and in full address mode,
channels A and B operate together. The bit functions in the DMACR registers differ according to
the transfer mode.
Short Address Mode:
• DMACR_0A, DMACR_0B, DMACR_1A, and DMARC_1B
Bit
7
6
5
Bit Name
DTSZ
DTID
RPE
DMA Control Registers (DMACRA and DMACRB)
Initial Value
0
0
0
R/W
R/W
R/W
R/W
Description
Data Transfer Size
Selects the size of data to be transferred at one
time.
0: Byte-size transfer
1: Word-size transfer
Data Transfer Increment/Decrement
Selects incrementing or decrementing of MAR
after every data transfer in sequential mode or
repeat mode. In idle mode, MAR is neither
incremented nor decremented.
0: MAR is incremented after a data transfer
•
•
1: MAR is decremented after a data transfer
•
•
Repeat Enable
Used in combination with the DTIE bit in
DMABCR to select the mode (sequential, idle, or
repeat) in which transfer is to be performed.
•
0: Transfer in sequential mode
1: Transfer in repeat mode
•
0: Transfer in sequential mode
1: Transfer in idle mode
When DTSZ = 0, MAR is incremented by 1
When DTSZ = 1, MAR is incremented by 2
When DTSZ = 0, MAR is decremented by 1
When DTSZ = 1, MAR is decremented by 2
When DTIE = 0 (no transfer end interrupt)
When DTIE = 1 (with transfer end interrupt)
Rev.6.00 Mar. 18, 2009 Page 219 of 980
Section 7 DMA Controller (DMAC)
REJ09B0050-0600