D12363VTE33 Renesas Electronics America, D12363VTE33 Datasheet - Page 700

• Manufacturer Part Number: D12363VTE33
• Description: MCU 3V 0K 120-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of D12363VTE33

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 84
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412363VTE33; HD6412363VTE33

Section 15 I
Bit Bit Name
4
3
2
Rev.6.00 Mar. 18, 2009 Page 640 of 980
REJ09B0050-0600
NACKF
STOP
AL
2
C Bus Interface2 (IIC2) (Option)
0
0
0
Initial Value R/W
R/W
R/W
R/W
Description
No acknowledge detection flag
[Setting condition]
When no acknowledge is detected from the receive device
in transmission while the ACKE bit in ICIER is 1
[Clearing condition]
When 0 is written in NACKF after reading NACKF = 1
Note: When NACKF = 1 is detected, NACKF must be
Stop condition detection flag
[Setting conditions]
•
•
[Clearing condition]
When 0 is written in STOP after reading STOP = 1
Arbitration Lost Flag
This flag indicates that arbitration was lost in master mode.
When two or more master devices attempt to seize the bus
at nearly the same time, if the I
differing from the data it sent, it sets AL to 1 to indicate that
the bus has been taken by another master.
•
•
[Clearing condition]
When 0 is written in AL/OVE after reading AL/OVE=1
[Setting conditions]
If the internal SDA and SDA pin disagree at the rise of
SCL in master transmit mode
When the SDA pin outputs high in master mode while a
start condition is detected
In master mode, when a stop condition is detected after
frame transfer
In slave mode, when a stop condition is detected after
the general call address or the first byte slave address,
next to detection of start condition, accords with the
address set in SAR
cleared to 0. Subsequent transmission in not made
until NACKF is cleared to 0.
2
C bus interface detects data