D12363VTE33 Renesas Electronics America, D12363VTE33 Datasheet - Page 255

• Manufacturer Part Number: D12363VTE33
• Description: MCU 3V 0K 120-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of D12363VTE33

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 84
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412363VTE33; HD6412363VTE33

Relationship between Chip Select (CS) Signal and Read (RD) Signal: Depending on the
system’s load conditions, the RD signal may lag behind the CS signal. An example is shown in
figure 6.47. In this case, with the setting for no idle cycle insertion (a), there may be a period of
overlap between the bus cycle A RD signal and the bus cycle B CS signal. Setting idle cycle
insertion, as in (b), however, will prevent any overlap between the RD and CS signals. In the
initial state after reset release, idle cycle insertion (b) is set.
Address bus
CS (area A)
CS (area B)
HWR, LWR
Data bus
Figure 6.46 Example of Idle Cycle Operation (Read after Write)
RD
φ
(a) No idle cycle insertion
T
(ICIS2 = 0)
1
Bus cycle A
Long output floating time
T
2
T
3
Bus cycle B
T
1
T
2
Data collision
Address bus
CS (area A)
CS (area B)
Data bus
HWR
RD
φ
Rev.6.00 Mar. 18, 2009 Page 195 of 980
T
(b) Idle cycle insertion
1
Bus cycle A
(ICIS2 = 1, initial value)
Section 6 Bus Controller (BSC)
T
2
T
3
Idle cycle
T
i
Bus cycle B
REJ09B0050-0600
T
1
T
2