D12363VTE33 Renesas Electronics America, D12363VTE33 Datasheet - Page 701

MCU 3V 0K 120-TQFP

D12363VTE33

Manufacturer Part Number
D12363VTE33
Description
MCU 3V 0K 120-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet

Specifications of D12363VTE33

Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
84
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
120-TQFP, 120-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Other names
HD6412363VTE33
HD6412363VTE33

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
D12363VTE33V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Bit Bit Name
1
0
15.3.6
SAR is an 8-bit readable/writable register that sets slave address. When the chip is in slave mode,
if the upper 7 bits of SAR match the upper 7 bits of the first frame received after a start condition,
the chip operates as the slave device.
Bit Bit Name
7 to
1
0
AAS
ADZ
SVA6 to
SVA0
Slave Address Register (SAR)
Initial Value R/W
0
0
Initial Value R/W
0
0
R/W
R/W
R/W
R/W
Description
Slave Address Recognition Flag
In slave receive mode, this flag is set to 1 if the first frame
following a start condition matches bits SVA6 to SVA0 in
SAR.
[Setting conditions]
[Clearing condition]
When 0 is written in AAS after reading AAS=1
General Call Address Recognition Flag
This bit is valid in slave receive mode.
[Setting condition]
When the general call address is detected in slave receive
mode
[Clearing conditions]
When 0 is written in ADZ after reading ADZ=1
Description
Slave Address 6 to 0
These bits set a unique address in bits SVA6 to SVA0,
differing form the addresses of other slave devices
connected to the I
Reserved
Though this bit can be read from or written to, the write
value should always be 0.
When the slave address is detected in slave receive
mode
When the general call address is detected in slave
receive mode.
Section 15 I
Rev.6.00 Mar. 18, 2009 Page 641 of 980
2
C bus.
2
C Bus Interface2 (IIC2) (Option)
REJ09B0050-0600

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