D12363VTE33 Renesas Electronics America, D12363VTE33 Datasheet - Page 612

• Manufacturer Part Number: D12363VTE33
• Description: MCU 3V 0K 120-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of D12363VTE33

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 84
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412363VTE33; HD6412363VTE33

Section 14 Serial Communication Interface (SCI, IrDA)
Rev.6.00 Mar. 18, 2009 Page 552 of 980
REJ09B0050-0600
Bit
4
3
2
Bit Name
RE
MPIE
TEIE
Initial Value
0
0
0
R/W
R/W
R/W
R/W
Description
Receive Enable
When this bit is set to 1, reception is enabled.
Serial reception is started in this state when a start
bit is detected in asynchronous mode or serial
clock input is detected in clocked synchronous
mode. SMR setting must be performed to decide
the transfer format before setting the RE bit to 1.
Clearing the RE bit to 0 does not affect the RDRF,
FER, PER, and ORER flags, which retain their
states.
Multiprocessor Interrupt Enable (enabled only
when the MP bit in SMR is 1 in asynchronous
mode)
When this bit is set to 1, receive data in which the
multiprocessor bit is 0 is skipped, and setting of
the RDRF, FER, and ORER status flags in SSR is
prohibited. On receiving data in which the
multiprocessor bit is 1, this bit is automatically
cleared and normal reception is resumed. For
details, refer to section 14.5, Multiprocessor
Communication Function.
When receive data including MPB = 0 in SSR is
received, receive data transfer from RSR to RDR,
receive error detection, and setting of the RDRF,
FER, and ORER flags in SSR , is not performed.
When receive data including MPB = 1 is received,
the MPB bit in SSR is set to 1, the MPIE bit is
cleared to 0 automatically, and generation of RXI
and ERI interrupts (when the TIE and RIE bits in
SCR are set to 1) and FER and ORER flag setting
is enabled.
Transmit End Interrupt Enable
When this bit is set to 1, TEI interrupt request is
enabled. TEI cancellation can be performed by
reading 1 from the TDRE flag in SSR, then
clearing it to 0 and clearing the TEND flag to 0, or
by clearing the TEIE bit to 0.