D12363VTE33 Renesas Electronics America, D12363VTE33 Datasheet - Page 94

MCU 3V 0K 120-TQFP

D12363VTE33

Manufacturer Part Number
D12363VTE33
Description
MCU 3V 0K 120-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet

Specifications of D12363VTE33

Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
84
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
120-TQFP, 120-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Other names
HD6412363VTE33
HD6412363VTE33

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
D12363VTE33V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 2 CPU
2.4.5
Reset exception handling loads the CPU's program counter (PC) from the vector table, clears the
trace (T) bit in EXR to 0, and sets the interrupt mask (I) bits in CCR and EXR to 1. The other
CCR bits and the general registers are not initialized. Note that the stack pointer (ER7) is
undefined. The stack pointer should therefore be initialized by an MOV.L instruction executed
immediately after a reset.
2.5
The H8S/2000 CPU can process 1-bit, 4-bit BCD, 8-bit (byte), 16-bit (word), and 32-bit
(longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2,
…, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two
digits of 4-bit BCD data.
2.5.1
Figure 2.9 shows the data formats of general registers.
Rev.6.00 Mar. 18, 2009 Page 34 of 980
REJ09B0050-0600
Initial Register Values
Data Formats
General Register Data Formats
Data Type
1-bit data
1-bit data
4-bit BCD data
4-bit BCD data
Byte data
Byte data
Figure 2.9 General Register Data Formats (1)
Register Number
RnH
RnL
RnH
RnL
RnH
RnL
MSB
Data Format
7
7
7
7
Upper
6 5 4 3 2
Don't care
Don't care
Don't care
4 3
Lower
1 0
LSB
0
0
0
MSB
7
7
7
7
Upper
6 5 4 3 2
Don't care
Don't care
Don't care
4 3
Lower
1 0
LSB
0
0
0

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