D12363VTE33 Renesas Electronics America, D12363VTE33 Datasheet - Page 193

MCU 3V 0K 120-TQFP

D12363VTE33

Manufacturer Part Number
D12363VTE33
Description
MCU 3V 0K 120-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet

Specifications of D12363VTE33

Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
84
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
120-TQFP, 120-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Other names
HD6412363VTE33
HD6412363VTE33

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
D12363VTE33V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
6.3.7
BCR is used for idle cycle settings, selection of the external bus released state protocol, enabling
or disabling of the write data buffer function, and enabling or disabling of WAIT pin input.
Bit
15
14
13
12
11
Bus Control Register (BCR)
Bit Name
BRLE
BREQOE
IDLC
ICIS1
Initial Value
0
0
0
1
1
R/W
R/W
R/W
R/W
R/W
R/W
Description
External Bus Release Enable
Enables or disables external bus release.
0: External bus release disabled
1: External bus release enabled
BREQO Pin Enable
Controls outputting the bus request signal
(BREQO) to the external bus master in the
external bus released state, when an internal
bus master performs an external address space
access, or when a refresh request is generated.
0: BREQO output disabled
1: BREQO output enabled
Reserved
Though this bit can be read from or written to,
the write value should always be 0.
Idle Cycle State Number Select
Specifies the number of states in the idle cycle
set by ICIS2, ICIS1, and ICIS0.
0: Idle cycle comprises 1 state
1: Idle cycle comprises 2 states
Idle Cycle Insert 1
When consecutive external read cycles are
performed in different areas, an idle cycle can be
inserted between the bus cycles.
0: Idle cycle not inserted
1: Idle cycle inserted
BREQ, BACK, and BREQO pins can be used
as I/O ports
BREQO pin can be used as I/O port
Rev.6.00 Mar. 18, 2009 Page 133 of 980
Section 6 Bus Controller (BSC)
REJ09B0050-0600

Related parts for D12363VTE33