D12363VTE33 Renesas Electronics America, D12363VTE33 Datasheet - Page 38

• Manufacturer Part Number: D12363VTE33
• Description: MCU 3V 0K 120-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of D12363VTE33

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 84
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412363VTE33; HD6412363VTE33

20.4 On-Board Programming Mode ......................................................................................... 748
20.5 Protection .......................................................................................................................... 778
20.6 Switching between User MAT and User Boot MAT ........................................................ 781
20.7 Programmer Mode ............................................................................................................ 782
20.8 Serial Communication Interface Specification for Boot Mode......................................... 782
20.9 Usage Notes ...................................................................................................................... 810
Section 21 Mask ROM
Section 22 Clock Pulse Generator
22.1 Register Descriptions ........................................................................................................ 813
22.2 Oscillator........................................................................................................................... 816
22.3 PLL Circuit ....................................................................................................................... 818
22.4 Frequency Divider ............................................................................................................ 819
22.5 Usage Notes ...................................................................................................................... 819
Section 23 Power-Down Modes
23.1 Register Descriptions ........................................................................................................ 826
23.2 Operation .......................................................................................................................... 830
Rev.6.00 Mar. 18, 2009 Page xxxvi of lviii
REJ09B0050-0600
20.3.2 Programming/Erasing Interface Parameter .......................................................... 735
20.3.3 Flash Vector Address Control Register (FVACR)............................................... 747
20.4.1 Boot Mode ........................................................................................................... 748
20.4.2 User Program Mode............................................................................................. 753
20.4.3 User Boot Mode................................................................................................... 764
20.4.4 Procedure Program and Storable Area for Programming Data ............................ 768
20.5.1 Hardware Protection ............................................................................................ 778
20.5.2 Software Protection.............................................................................................. 779
20.5.3 Error Protection.................................................................................................... 779
22.1.1 System Clock Control Register (SCKCR) ........................................................... 814
22.1.2 PLL Control Register (PLLCR)........................................................................... 815
22.2.1 Connecting a Crystal Oscillator ........................................................................... 816
22.2.2 External Clock Input ............................................................................................ 817
22.5.1 Notes on Clock Pulse Generator .......................................................................... 819
22.5.2 Notes on Oscillator .............................................................................................. 820
22.5.3 Notes on Board Design ........................................................................................ 820
23.1.1 Standby Control Register (SBYCR) .................................................................... 826
23.1.2 Module Stop Control Registers H and L (MSTPCRH, MSTPCRL).................... 828
23.1.3 Extension Module Stop Control Registers H and L
23.2.1 Clock Division Mode........................................................................................... 830
(EXMSTPCRH, EXMSTPCRL) ......................................................................... 829
....................................................................................................... 811
...................................................................................... 823
.................................................................................. 813