D12363VTE33 Renesas Electronics America, D12363VTE33 Datasheet - Page 305

• Manufacturer Part Number: D12363VTE33
• Description: MCU 3V 0K 120-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of D12363VTE33

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 84
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412363VTE33; HD6412363VTE33

Transfer Mode
Short
address
mode
Full
address
mode
Single address mode
•
•
•
Normal mode
(1) Auto-request
•
•
•
(2) External request
•
•
Block transfer mode
•
•
•
•
1-byte or 1-word transfer
for a single transfer
request
1-bus cycle transfer by
means of DACK pin
instead of using address
for specifying I/O
Sequential mode, idle
mode, or repeat mode
can be specified
Transfer request is
internally held
Number of transfers (1 to
65,536) is continuously
sent
Burst/cycle steal transfer
can be selected
1-byte or 1-word transfer
for a single transfer
request
Number of transfers: 1 to
65,536
Transfer of 1-block, size
selected for a single
transfer request
Number of transfers: 1 to
65,536
Source or destination can
be selected as block area
Block size: 1 to 256 bytes
or word
Transfer Source
•
•
•
•
•
•
•
•
•
•
•
•
TPU channel 0 to 5
compare match/input
capture A interrupt
SCI transmission
complete interrupt
SCI reception
complete interrupt
A/D converter
conversion end
interrupt
External request
Auto-request
External request
TPU channel 0 to 5
compare match/input
capture A interrupt
SCI transmission
complete interrupt
SCI reception
complete interrupt
A/D converter
conversion end
interrupt
External request
Rev.6.00 Mar. 18, 2009 Page 245 of 980
Section 7 DMA Controller (DMAC)
Remarks
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•
•
•
•
•
Up to 4 channels can
operate independently
External request
applies to channel B
only
Single address mode
applies to channel B
only
Max. 2-channel
operation, combining
channels A and B
REJ09B0050-0600