D12363VTE33 Renesas Electronics America, D12363VTE33 Datasheet - Page 336

MCU 3V 0K 120-TQFP

D12363VTE33

Manufacturer Part Number
D12363VTE33
Description
MCU 3V 0K 120-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet

Specifications of D12363VTE33

Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
84
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
120-TQFP, 120-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Other names
HD6412363VTE33
HD6412363VTE33

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
D12363VTE33V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 7 DMA Controller (DMAC)
Figure 7.27 shows a transfer example in which TEND output is enabled and word-size single
address mode transfer (read) is performed from external 8-bit, 2-state access space to an external
device.
A byte or word transfer is performed for a single transfer request, and after the transfer, the bus is
released. While the bus is released, one or more bus cycles are executed by the CPU or DTC.
Rev.6.00 Mar. 18, 2009 Page 276 of 980
REJ09B0050-0600
Address bus
Address bus
DACK
TEND
RD
φ
Figure 7.27 Example of Single Address Mode (Word Read) Transfer
DACK
TEND
Figure 7.26 Example of Single Address Mode Transfer (Byte Read)
release
RD
Bus
φ
release
Bus
DMA read
DMA read
release
Bus
release
Bus
DMA read
DMA read
release
Bus
DMA read
release
Bus
release
Bus
DMA read
Last transfer
DMA read
Last transfer
cycle
cycle
DMA
dead
release
DMA
dead
Bus
release
Bus

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